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Three-Dimensional Integration of Network-on-Chip
due to the incorporation of huge number of cores on single silicon die. The
3D IC technology that stacks multiple layers of active silicon using special
vertical interconnects, known as through-silicon vias, is an attractive solution
to this problem. A survey of existing 3D fabrication technologies were carried out by Beyne (2006). The pros and cons of going in vertical direction
were investigated by Davis et al. (2005). Three-dimensional IC has higher
integration density and smaller form factor. However, due to low thermal
conductivity of dielectric materials inserted between two adjacent layers,
high-temperature zones will get created, particularly in layers away from
heat sink. This will necessitate better cooling arrangement. Dissipated heat at
any layer is conducted to the ambient through vertical and horizontal flows.
However, larger length of a wafer than its thickness makes vertical heat flow
to be dominant. Figure 11.1a shows a cross section of vertically stacked tiles
for an n-layer 3D IC. Each layer consists of a silicon layer (bottom), an interlayer dielectric (ILD) and Cu layer, and a glue layer. Figure 11.1b depicts the
dissipated heat of a tile at layer i that flows to layer (i − 1) through silicon at
layer i, glue at layer (i − 1), and insulator at layer (i − 1). This unequal heat dissipation has negative impacts on system reliability and performance. Over
the past few years, 3D IC has evolved into a design paradigm. The salient
features and important challenges of 3D integration are briefly reviewed in
Sections 11.2.1 and 11.2.2.
11.2.1 Opportunities of 3D integration
• Decrease in interconnect length: A common metric to characterize
the longest interconnect is to assume that its length is equal to
the summation of length and breadth of the die. Hence, for a 2D
square-shaped die of area A, the length of the longest interconnect
is L 2D max = 2√A. Implementing the same design in n-layered 3D IC
requires an area of (A/n) in each plane keeping the total area of the
system remains same with 2D case. Hence, for an n-layered 3D IC,
the length of the longest interconnect is L 3D max = 2√(A/n), considering that each plane is square in shape. The actual benefit of 3D
IC relies on the fact that the relatively long wires (approximately in
millimeters) of 2D IC can be replaced by the interlayer TSVs whose
lengths are about tens of microns. This considerable decrease in
interconnect length minimizes the link delay and link energy consumption significantly and at the same time more immunity to
noise (Topol et al. 2006; Flic and Bertozzi 2010). Due to increased
connectivity, 3D ICs have the potential for enhancing system performance, achieving better functionality, and for producing higher
packaging density compared to its traditional 2D counterpart
(Davis et al. 2005).
• Heterogeneous and multifunctional SoC design: Unlike 2D planer
ICs, 3D ICs offer increased system integration either by increasing
Three-Dimensional Integration of Network-on-Chip
due to the incorporation of huge number of cores on single silicon die. The
3D IC technology that stacks multiple layers of active silicon using special
vertical interconnects, known as through-silicon vias, is an attractive solution
to this problem. A survey of existing 3D fabrication technologies were carried out by Beyne (2006). The pros and cons of going in vertical direction
were investigated by Davis et al. (2005). Three-dimensional IC has higher
integration density and smaller form factor. However, due to low thermal
conductivity of dielectric materials inserted between two adjacent layers,
high-temperature zones will get created, particularly in layers away from
heat sink. This will necessitate better cooling arrangement. Dissipated heat at
any layer is conducted to the ambient through vertical and horizontal flows.
However, larger length of a wafer than its thickness makes vertical heat flow
to be dominant. Figure 11.1a shows a cross section of vertically stacked tiles
for an n-layer 3D IC. Each layer consists of a silicon layer (bottom), an interlayer dielectric (ILD) and Cu layer, and a glue layer. Figure 11.1b depicts the
dissipated heat of a tile at layer i that flows to layer (i − 1) through silicon at
layer i, glue at layer (i − 1), and insulator at layer (i − 1). This unequal heat dissipation has negative impacts on system reliability and performance. Over
the past few years, 3D IC has evolved into a design paradigm. The salient
features and important challenges of 3D integration are briefly reviewed in
Sections 11.2.1 and 11.2.2.
11.2.1 Opportunities of 3D integration
• Decrease in interconnect length: A common metric to characterize
the longest interconnect is to assume that its length is equal to
the summation of length and breadth of the die. Hence, for a 2D
square-shaped die of area A, the length of the longest interconnect
is L 2D max = 2√A. Implementing the same design in n-layered 3D IC
requires an area of (A/n) in each plane keeping the total area of the
system remains same with 2D case. Hence, for an n-layered 3D IC,
the length of the longest interconnect is L 3D max = 2√(A/n), considering that each plane is square in shape. The actual benefit of 3D
IC relies on the fact that the relatively long wires (approximately in
millimeters) of 2D IC can be replaced by the interlayer TSVs whose
lengths are about tens of microns. This considerable decrease in
interconnect length minimizes the link delay and link energy consumption significantly and at the same time more immunity to
noise (Topol et al. 2006; Flic and Bertozzi 2010). Due to increased
connectivity, 3D ICs have the potential for enhancing system performance, achieving better functionality, and for producing higher
packaging density compared to its traditional 2D counterpart
(Davis et al. 2005).
• Heterogeneous and multifunctional SoC design: Unlike 2D planer
ICs, 3D ICs offer increased system integration either by increasing