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Network-on-Chip
modulator should exhibit performance characteristics that ensure
that the optical links outperform the electrical interconnect (Chen et al.
2007). The integration of silicon photonic devices with CMOS ICs for
chip-to-chip communication became commercially available (Gunn
2006). This remarkable achievement has paved the path to design a 3D
IC-based photonic NoC where the top layer is used for high-bandwidth
circuit-switched optical network and the bottom layer is used for lowbandwidth packet-switched electronic network (Ye et al. 2009). The
cores are placed at the electronic layer and are connected to the optical layer through TSVs and via electro-optical/optoelectronic interfaces.
The header information (source and destination addresses) is routed
through the electronic layer to set up the optical path between source
and destination. The payload information is transmitted along the
reserved optical path at very high speed without buffering, whereas the
tailer is used to release the path. It leverages two important advantages
of optical communication: (1) the energy dissipation is essentially independent of the bit rate and (2) the energy dissipation is independent
of transmission distance. Hence, photonic NoCs can deliver very high
bandwidth and offer a low-power communication medium (Carloni
et al. 2009). Photonic NoC research is now growing extensively and a
number of implementations have already been reported in literature
(Vantrease et al. 2008; Cianchetti et al. 2009; Pan et al. 2009). Gu et al.
(2009) proposed the design of optical router for photonic NoC.
3. Wireless NoC: Another promising alternative to two-dimensional
(2D) NoC is the use of radio frequency (RF)/wireless interconnects
for signal transmission. Unlike photonic and 3D NoCs, NoC with
RF interconnects can be built using existing 2D CMOS technology.
But it requires long on-chip transmission lines that serve as wave
guides. It achieves an on-chip effective speed of light signal propagation and also saves power consumption (Chang et al. 2008).
This chapter describes the 3D integration of NoC in detail. The rest of the
chapter is organized as follows: Section 11.2 describes the pros and cons of
3D integration. Section 11.3 describes the design and evaluation of 3D NoC
architecture. Performance and cost evaluation of 3D NoC architecture is performed with self-similar and application-specific traffic and compared with
that of 2D NoC counterpart. Finally, Section 11.4 summarizes this chapter.
11.2 3D Integration: Pros and Cons
In the many-core era, integrating large number of cores on a 2D IC has limited floorplanning choices. Although the size of an individual core is reduced
up to a certain level due to technology shrinking, chip sizes may increase