11
Three-Dimensional Integration
of Network-on-Chip
11.1 Introduction
On-chip networks can enhance the communication bandwidth among the
individual functional blocks of an integrated system, but at the same time,
speed and power consumed by the networks are eventually limited by the
delay of the wires connecting the network links. In the upcoming technologies, it is hardly sufficient to support the ever-increasing performance demand,
without raising the energy consumption. Since long wire is the major bottleneck in designing a network-on-chip (NoC)-based system in deep submicron
(DSM) technology, in terms of performance, speed, and energy consumption,
researchers are trying to find out the alternatives to it. Current-mode signaling (Bashirullah et al. 2003; Nigussie et al. 2007), wave pipelined interconnects
(Deodhar and Davis 2005), and low-swing signaling (Zhang et al. 2000) are the
incremental techniques to address this problem to some extent. Three emerging technologies have been envisioned to address the above issues: threedimensional (3D) NoC, photonic NoC, and wireless NoC (Carloni et al. 2009).
1. 3D NoC: After the advent of 3D integrated circuit (IC), as it exhibits higher performance and lesser energy consumption, researchers
have amalgamated NoC with 3D IC that gives birth to a new technology, 3D NoC. In 3D IC, multiple silicon layers are integrated vertically in a stack where interlayer distance is taken as tens of microns.
Copper through-silicon via (TSV) is the mostly used interconnect
between two adjacent silicon layers (Savidis et al. 2010). Copper wire
is also used as an intralayer interconnect.
2. Photonic NoC: The major challenges in adopting photonic communication in NoC design are flit buffering and header processing
(Shacham et al. 2007; Petracca et al. 2008). Moreover, integrating a modulator and detector onto the silicon within a standard
complementary metal oxide semiconductor (CMOS) process is also
a difficult task (Haurylau et al. 2006). In addition, the detector and
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