Reconfigurable Network-on-Chip Design
297
TABLe 10.4
Area Overheads of Different Architectures
Number of Cores (M × N)
Simple Two-Core per Router
Mesh (without
Reconfiguration)
16 (2 × 4)
0.129
32 (4 × 4)
0.130
64 (4 × 8)
0.130
128 (8 × 8)
0.130
256 (8 × 16)
0.130
512 (16 × 16)
0.130
Reconfigurable
Architecture
0.131
0.131
0.131
0.131
0.131
0.131
applications. This is justified as the applications constitute a full system.
Further, the reconfiguration is assumed to be static in nature. Thus, for a
task, the core accomplishing it is known at the system design time itself. Each
task is bound to a fixed core. Cores may be multifunctional; thus, a number
of tasks may be bound to a single core. It may be noted that dynamic task
allocation to cores in NoC can also be performed for the proposed topology; however, this chapter does not address this issue. We rather restrict our
attention to show the promise of the proposed architecture for a multiapplication environment with core sharing among applications.
Once the core for each application task has been discussed, the applications
can be viewed as a set of core graphs defined next. Each core performs one
or more tasks of one or more applications. The communication requirement
of a pair of cores for each application is computed from the communication
requirements of the corresponding communicating tasks in the application
bound to these cores. All such task communications are added to get communication between the pair of cores. For application A i , its core graph G i
consists of a number of nodes equal to the number of cores needed for A i .
There is an edge between the nodes c ij and c ik if there are communications
between cores j and k in application A i . The edge has a weight equal to the
corresponding bandwidth requirement.
The design flow of the proposed reconfigurable NoC synthesis procedure
(shown in Figure 10.4) can be divided into following three stages:
• Construction of combined core graph (CCG)
• Mapping of cores in CCG to the mesh network
• Configuration generation for each application
Each stage is described in Sections 10.3.5.1 through 10.3.5.3.