296
Network-on-Chip
⎡ (Number of four-port routers)× (Area of four-port routers ) ⎤
⎢
⎥
⎢ + (N Number of five-port routers )×(Area of five-port routers) ⎥
⎢ + + (N
(
⎥
umber of six-port routers )× Area of six-port routers )
⎢
⎥
⎢ + (N Number of 4:1 multiplexers )× (Area of 4:1 multiplexers ) ⎥
⎢
⎥
⎢ + (Nu umber of 2:1 multiplexers )×(Area of 2:1 multiplexers ) ⎥
⎢ ⎢ (
⎥
+ Num mber of four-input two-output selection logic blocks )
⎢
⎥
⎢ ×(Area of four-input two-output selection logic blocks
e
)
⎥
⎢
⎥
+
⎢ (Numbe er of eight-input two-output selection logic blocks ) ⎥
⎣ ⎢ ×(Area of eight-input two-output selection logic blocks ) ⎥ ⎦
Total core area
⎡ 259761× ( M − 2)(N − 2) + 2 × 190930 × ( M + N − 4) + 4 × 80305. 5 ⎤
⎢
⎥
⎢ + 3237 × ( M − 1) ( (N − 1) + 1618 .5 × ( M + N − 2) + 809. 25
⎥
= ⎢
⎥
⎢ ⎣
×( M − 1)(N − 1) + 404. 62 × ( M + N − 2)
⎦ ⎥ ⎦
2MNx
259761× ( M − 2 )( N − 2 ) + 381860 × ( M + N − 4 ) + 4046. 25
× ( M − 1)(N − 1) + 2023. 12 2 × ( M + N − 2)
=
2MNx
The area overheads of different architectures are shown in Table  10.4. It
can be seen that the area overhead of the proposed reconfigurable scheme
is 0.1% more than a simple mesh without reconfiguration. Thus, the proposed architecture is a feasible one and supports reconfiguration. The
reconfiguration procedure has to identify the select lines of multiplexers (implemented by the configuration manager at the application layer)
which will decide the connection between cores and routers for each
application.
10.3.5 Design Flow
The strategy to design a reconfigurable NoC for a set of given applications,
using the architecture proposed, has been discussed in this section. It is
assumed that the applications have a number of tasks common between
themselves; however, the communication pattern may change across the