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Ogras, U. Y., Hu, J., and Marculescu, R. 2005. Key research problems in NoC design:
A holistic perspective. Proceedings of the IEEE/ACM/IFIP International Conference
on Hardware/Software Codesign and System Synthesis, pp. 69–74, Jersey City, NJ.
Pande, P. P., Grecu, C., Jones, M., Ivanov, A., and Saleh, R. 2005. Performance evaluation and design trade-offs for MP-SOC interconnect architectures. IEEE
Transactions on Computers, vol. 54, no. 8, pp. 1025–1040.
Pavlidis, V. F. and Friedman, E. G. 2007. 3-D Topologies for networks-on-chip. IEEE
Transactions on VLSI Systems, vol. 15, no. 10, pp. 1081–1090.
Rijpkema, E., Goossens, K. G. W., and Radulescu, A. 2003. Trade offs in the design
of a router with both guaranteed and best-effort services for network on chip
(extended version). IEE Proceedings of the Computers and Digital Techniques, vol. 150,
no. 5, pp. 294–302, Munich, Germany.
Rostislav, D., Vishnyakov, V., Friedman, E., and Ginosar, R. 2005.An asynchronous router
for multiple service levels networks on chip. Proceedings of the IEEE International
Symposium on Asynchronous Circuits and Systems, pp. 44–53, New York.
Salminen, E., Kulmala, A., and Hamalainen, T. D. 2008. Survey of network-on-chip
proposals. White Paper,
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/File/SCC_Sympossium_Mar162010_GML_final.pdf.
Sylvester, D. and Keutzer, K. 2000. A global wiring paradigm for deep submicron
design. IEEE Transactions on Computer Aided Design of Integrated Circuits and
Systems, vol. 19, no. 2, pp. 242–252.
Topol, A. W., Tulipe, D. C. L., Shi, L., Frank, D. J., Bernstein, K., Steen, S. E., Kumar,
A., Singco, G. U., Young, A. M., Guarini, K. W., and Ieong, M. 2006. Threedimensional integrated circuits. IBM Journal of Research and Development, vol. 50,
nos. 4/5, p. 491.
Vangal, S. R., Howard, J., Ruhl, G., Dighe, S., Wilson, H., Tschanz, J., Finan, D., Singh, A.,
Jacob, T., Jain, S., Erraguntla, V., Roberts, C., Hoskote, Y., Borkar, N., and Borkar,
S. 2008. An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS. IEEE
Journal of Solid-State Circuits, vol. 43, no. 1, pp. 29–41.
Wentzlaff, D., Griffin, P., Hoffmann, H., Bao, L., Edwards, B., Ramey, C., Mattina, M.,
Miao, C. C., Brown, J. F., and Agarwal, A. 2007. On-chip interconnection architecture of the TILE processor. IEEE Micro, vol. 27, no. 5, pp. 15–31.
Zhang, Y. P., Jeong, T., Chen, F., and Wu, H. 2006. A study of the on-chip interconnection network for the IBM Cyclops64 multi-core architecture. Proceedings of the
IEEE International Parallel and Distributed Symposium, Rhode Island.
Network-on-Chip
platform. Proceedings of the IEEE International Solid-State Circuits Conference, San
Francisco, CA.
Lee, K., Lee, S. J., and Yoo, H. J. 2006. Low-power network-on-chip for highperformance SoC design. IEEE Transactions on Very Large Scale Integration (VLSI)
Systems, vol. 14, no. 2, pp. 148–160.
Marculescu, R., Ogras, U. Y., Peh, L. S., Jerger, N. E., and Hoskote, Y. 2009. Outstanding
research problems in NoC design: Systems, microarchitecture, and circuit perspectives. IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, vol. 28, no. 1, pp. 3–21.
Mullins, R. D. 2009. On-chip network bibliography. http://www.cl.cam.ac.uk/~rdm34
/onChipNetBib/onChipNetwork.pdf.
Ogras, U. Y., Hu, J., and Marculescu, R. 2005. Key research problems in NoC design:
A holistic perspective. Proceedings of the IEEE/ACM/IFIP International Conference
on Hardware/Software Codesign and System Synthesis, pp. 69–74, Jersey City, NJ.
Pande, P. P., Grecu, C., Jones, M., Ivanov, A., and Saleh, R. 2005. Performance evaluation and design trade-offs for MP-SOC interconnect architectures. IEEE
Transactions on Computers, vol. 54, no. 8, pp. 1025–1040.
Pavlidis, V. F. and Friedman, E. G. 2007. 3-D Topologies for networks-on-chip. IEEE
Transactions on VLSI Systems, vol. 15, no. 10, pp. 1081–1090.
Rijpkema, E., Goossens, K. G. W., and Radulescu, A. 2003. Trade offs in the design
of a router with both guaranteed and best-effort services for network on chip
(extended version). IEE Proceedings of the Computers and Digital Techniques, vol. 150,
no. 5, pp. 294–302, Munich, Germany.
Rostislav, D., Vishnyakov, V., Friedman, E., and Ginosar, R. 2005.An asynchronous router
for multiple service levels networks on chip. Proceedings of the IEEE International
Symposium on Asynchronous Circuits and Systems, pp. 44–53, New York.
Salminen, E., Kulmala, A., and Hamalainen, T. D. 2008. Survey of network-on-chip
proposals. White Paper,
© OCP-IP ns2.ocpip-server.com/uploads/documents/
OCP-IP_Survey_of_NoC_Proposals_White_Paper_April_2008.pdf.
SCC. 2010. Single-chip cloud computer. http://techresearch.intel.com/UserFiles/en-us
/File/SCC_Sympossium_Mar162010_GML_final.pdf.
Sylvester, D. and Keutzer, K. 2000. A global wiring paradigm for deep submicron
design. IEEE Transactions on Computer Aided Design of Integrated Circuits and
Systems, vol. 19, no. 2, pp. 242–252.
Topol, A. W., Tulipe, D. C. L., Shi, L., Frank, D. J., Bernstein, K., Steen, S. E., Kumar,
A., Singco, G. U., Young, A. M., Guarini, K. W., and Ieong, M. 2006. Threedimensional integrated circuits. IBM Journal of Research and Development, vol. 50,
nos. 4/5, p. 491.
Vangal, S. R., Howard, J., Ruhl, G., Dighe, S., Wilson, H., Tschanz, J., Finan, D., Singh, A.,
Jacob, T., Jain, S., Erraguntla, V., Roberts, C., Hoskote, Y., Borkar, N., and Borkar,
S. 2008. An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS. IEEE
Journal of Solid-State Circuits, vol. 43, no. 1, pp. 29–41.
Wentzlaff, D., Griffin, P., Hoffmann, H., Bao, L., Edwards, B., Ramey, C., Mattina, M.,
Miao, C. C., Brown, J. F., and Agarwal, A. 2007. On-chip interconnection architecture of the TILE processor. IEEE Micro, vol. 27, no. 5, pp. 15–31.
Zhang, Y. P., Jeong, T., Chen, F., and Wu, H. 2006. A study of the on-chip interconnection network for the IBM Cyclops64 multi-core architecture. Proceedings of the
IEEE International Parallel and Distributed Symposium, Rhode Island.