11
Introduction
Bjerregaard, T. and Sparsoe, J. 2005. A router architecture for connection-oriented
service guarantees in the MANGO clockless network-on-chip. Proceedings of the
Design, Automation and Test in Europe Conference, pp. 1226–1231, Munich, Germany.
Coppola, M., Locatelli, R., Maruccia, G., Pieralisi, L., and Scandurra, A. 2004. Spidergon:
A novel on-chip communication network. Proceedings of the International Symposium on System on Chip, p. 15, Tampere, Finland.
Dally, W. J. and Towles, B. 2004. Principles and Practices of Interconnection Networks.
Morgan Kaufmann Publishers, San Francisco, CA.
Davis, W. R., Wilson, J., Mick, S., Xu, J., Hua, H., Mineo, C., Sule, A. M., Steer, M., and
Franzon, P. D. 2005. Demystifying 3D ICs: The pros and cons of going vertical.
IEEE Design and Test of Computers, vol. 22, no. 6, pp. 498–510.
Duato, J., Yalamanchili, S., and Ni, L. 2003. Interconnection Networks: An Engineering
Approach. Morgan Kaufmann Publishers, San Francisco, CA.
Feero, B. S. and Pande, P. P. 2009. Networks-on-chip in a three dimensional environment: A performance evaluation. IEEE Transactions on Computers, vol. 58, no. 1,
pp. 32–45.
Flic, J. and Bertozzi, D. 2010. Designing Network On-Chip Architectures in the Nanoscale
Era. Chapman & Hall/CRC Computational Science, Boca Raton, FL.
Gratz, P., Changkyu, K., McDonald, R., Keckler, S. W., and Burger, D. 2006. Implementation and evaluation of on-chip network architectures. Proceedings of the
IEEE International Conference on Computer Design, pp. 477–484, San Jose, CA.
Grecu, C., Pande, P. P., Ivanov, A., and Saleh, R. 2004. Structured interconnect architecture: A solution for the non-scalability of bus-based SoCs. Proceedings of the
ACM Great Lakes Symposium on VLSI, pp. 192–195, Boston, MA.
ITRS. 2001. International technology roadmap for semiconductors. Technical report,
International Technology Roadmap for Semiconductors.
Jantsch, A. and Tenhunen, H. 2003. Networks on Chip. Kluwer Academic Publishers,
Boston, MA.
Jerger, N. E. and Peh, L. S. 2009. On-Chip Networks (Synthesis Lectures on Computer
Architectures). Morgan & Claypool Publishers, San Rafael, CA.
Kapur, P., Chandra, G., McVittie, J. P., and Saraswat, K. C. 2002. Technology and reliability constrained future copper interconnects—Part II: Performance implications. IEEE Transactions on Electron Devices, vol. 49, no. 4, pp. 598–604.
Kariniemi, H. 2006. On-line reconfigurable extended generalized fat tree networkon-chip for multiprocessor system-on-chip circuits. PhD dissertation, Tampere
University of Technology, Finland.
Kavaldjiev, N., Smit, G. J. M., Jansen, P. G., and Wolkotte, P. T. 2006. A virtual channel
network-on-chip for GT and BE traffic. Proceedings of the IEEE Computer Society
Annual Symposium on Emerging VLSI Technologies and Architectures, Karlsruhe,
Germany.
Kumar, A., Kundu, P., Singh, A. P., Peh, L. S., and Jha, N. K. 2007. A 4.6Tbits/s
3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS.
Proceedings of the IEEE International Conference on Computer Design, pp. 63–70,
Lake Tahoe, CA.
Lattard, D., Beigne, E., Clermidy, F., Durand, Y., Lemaire, R., Vivet, P., and Berens, F.
2008. A reconfigurable baseband platform based on an asynchronous networkon-chip. IEEE Journal of Solid-State Circuits, vol. 43, no. 1, pp. 223–235.
Lee, K., Lee, S. J., Kim, S. E., Chol, H. M., Kim, D., Kim, S., Lee, M. W., and Yoo, H. J.
2004. A 51mW 1.6GHz on-chip network for low-power heterogeneous SoC
Introduction
Bjerregaard, T. and Sparsoe, J. 2005. A router architecture for connection-oriented
service guarantees in the MANGO clockless network-on-chip. Proceedings of the
Design, Automation and Test in Europe Conference, pp. 1226–1231, Munich, Germany.
Coppola, M., Locatelli, R., Maruccia, G., Pieralisi, L., and Scandurra, A. 2004. Spidergon:
A novel on-chip communication network. Proceedings of the International Symposium on System on Chip, p. 15, Tampere, Finland.
Dally, W. J. and Towles, B. 2004. Principles and Practices of Interconnection Networks.
Morgan Kaufmann Publishers, San Francisco, CA.
Davis, W. R., Wilson, J., Mick, S., Xu, J., Hua, H., Mineo, C., Sule, A. M., Steer, M., and
Franzon, P. D. 2005. Demystifying 3D ICs: The pros and cons of going vertical.
IEEE Design and Test of Computers, vol. 22, no. 6, pp. 498–510.
Duato, J., Yalamanchili, S., and Ni, L. 2003. Interconnection Networks: An Engineering
Approach. Morgan Kaufmann Publishers, San Francisco, CA.
Feero, B. S. and Pande, P. P. 2009. Networks-on-chip in a three dimensional environment: A performance evaluation. IEEE Transactions on Computers, vol. 58, no. 1,
pp. 32–45.
Flic, J. and Bertozzi, D. 2010. Designing Network On-Chip Architectures in the Nanoscale
Era. Chapman & Hall/CRC Computational Science, Boca Raton, FL.
Gratz, P., Changkyu, K., McDonald, R., Keckler, S. W., and Burger, D. 2006. Implementation and evaluation of on-chip network architectures. Proceedings of the
IEEE International Conference on Computer Design, pp. 477–484, San Jose, CA.
Grecu, C., Pande, P. P., Ivanov, A., and Saleh, R. 2004. Structured interconnect architecture: A solution for the non-scalability of bus-based SoCs. Proceedings of the
ACM Great Lakes Symposium on VLSI, pp. 192–195, Boston, MA.
ITRS. 2001. International technology roadmap for semiconductors. Technical report,
International Technology Roadmap for Semiconductors.
Jantsch, A. and Tenhunen, H. 2003. Networks on Chip. Kluwer Academic Publishers,
Boston, MA.
Jerger, N. E. and Peh, L. S. 2009. On-Chip Networks (Synthesis Lectures on Computer
Architectures). Morgan & Claypool Publishers, San Rafael, CA.
Kapur, P., Chandra, G., McVittie, J. P., and Saraswat, K. C. 2002. Technology and reliability constrained future copper interconnects—Part II: Performance implications. IEEE Transactions on Electron Devices, vol. 49, no. 4, pp. 598–604.
Kariniemi, H. 2006. On-line reconfigurable extended generalized fat tree networkon-chip for multiprocessor system-on-chip circuits. PhD dissertation, Tampere
University of Technology, Finland.
Kavaldjiev, N., Smit, G. J. M., Jansen, P. G., and Wolkotte, P. T. 2006. A virtual channel
network-on-chip for GT and BE traffic. Proceedings of the IEEE Computer Society
Annual Symposium on Emerging VLSI Technologies and Architectures, Karlsruhe,
Germany.
Kumar, A., Kundu, P., Singh, A. P., Peh, L. S., and Jha, N. K. 2007. A 4.6Tbits/s
3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS.
Proceedings of the IEEE International Conference on Computer Design, pp. 63–70,
Lake Tahoe, CA.
Lattard, D., Beigne, E., Clermidy, F., Durand, Y., Lemaire, R., Vivet, P., and Berens, F.
2008. A reconfigurable baseband platform based on an asynchronous networkon-chip. IEEE Journal of Solid-State Circuits, vol. 43, no. 1, pp. 223–235.
Lee, K., Lee, S. J., Kim, S. E., Chol, H. M., Kim, D., Kim, S., Lee, M. W., and Yoo, H. J.
2004. A 51mW 1.6GHz on-chip network for low-power heterogeneous SoC