10
Network-on-Chip
topology with a flit size of 32 bits. The NIs synchronize the clocked open core
protocol (OCP) interfaces to the clock-less network in a GALS fashion and the
overall network is running at 795 MHz in 130-nm technology at the register transfer level (RTL) level. Silistix Inc. has introduced its industry leading
asynchronous NoC, CHAINworks (Rostislav et al. 2005), for the design and synthesis of complex devices. FAUST (Lattard et al. 2008), another asynchronous
NoC implemented in 130-nm technology for telecom requirements, uses the
2D mesh technology with a flit size of 32 bits. In the work of Salminen et al.
(2008), a list of NoC proposals has been presented in a tabular form that effectively characterizes many of the NoCs that are not covered here.
1.5 Summary
NoC is a very active research field with many practical applications in
industry as it is expected to be an efficient communication backbone of nextgeneration many-core-based SoCs. This chapter focuses on the upcoming
technology trends and the needs of NoC in designing many-core-based
SoCs. It also briefly covers different horizons of research in the field of NoC
design. Finally, a set of NoCs that has been designed till date from the industry and academia has also been covered.
The research dimensions of NoC noted in this chapter have been taken up
in subsequent chapters and discussed in detail.
References
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