9
Introduction
supporting highly local traffic inside a node, Intel has introduced single-chip
cloud computer (SCC) having 48 cores (SCC 2010). Two cores are connected
with each router of a 6 × 4 2D mesh. The operating frequency of each core is
1 GHz, whereas the routers are targeted to work with 2 GHz in 45-nm technology. The routers have been implemented with eight virtual channels and fourcycle latency. The link width has been taken as 128 bits. ST Microelectronics
have implemented STNoC (Coppola et al. 2004), a spidergon topology-based
NoC that follows a credit-based flow control. Philips have developed a topology-independent NoC, Æthereal (Rijpkema et al. 2003), for supporting guaranteed throughput (GT) and best effort (BE) services. The router has been
implemented by an input-buffering scheme with first-in first-out (FIFO)
depth of 8 bits and width of 32 bits. It uses a standard credit-based end-toend flow control. Both the routers and the NI operate at 500 MHz in 130-nm
technology at the layout level. Arteris is another custom NoC that operates at
750 MHz in 90-nm technology (Arteris 2005). It has a set of configuration and
modeling tools—NoC compiler, NoC verifier, and NoC explorer—for getting
optimized performance and power result for any application.
Kumar et al. (2007) implemented a 36-core shared memory chip multiprocessing (CMP) system in 65-nm technology targeting 3.6 GHz router with
single-cycle latency. The cores are connected in a 6 × 6 2D mesh having a flit size
of 128 bits. The router has 12 unreserved virtual channels and 1 reserved virtual
channel for each of three message classes. It has been implemented with singlestage pipelining. Lee et al. (2004) implemented a hierarchical star-connected
on-chip network by using a 16:1 serialized link. The routers and cores operate
at 1.6 GHz and 100 MHz, respectively, in 180-nm technology. The authors have
also implemented a custom NoC, Slim-spider (Lee et al. 2006), ensuring lowpower consumption where each router operates at 1.6 GHz in 180-nm technology taking a flit size of 8 bits. Adriahantenaina et al. (2003) implemented a fat
tree-based NoC, scalable, programmable, integrated network (SPIN), in 130-nm
technology taking a flit size of 32 bits. The operating frequency of routers is
found to be 200 MHz at the layout level. Another fat tree-based NoC, extended
generalized fat-tree (XGFT) (Kariniemi et al. 2006), uses a flit size of 32 bits and
operates at 400 MHz. Xpipes (Bertozzi et al. 2005), a custom NoC, consists of
soft macros of switches, NIs, and links. It takes a flit width of 32 bits and supports error detection and retransmission. Kavaldjiev et al. (2006) modified the
traditional virtual channel router and the new router is working at 500 MHz
in 180-nm technology supporting the 2D mesh topology with 16-bit flit size.
Pande et al. (2005) reported that the area overhead of the routers is reasonably low compared to that of full SoC. Feero and Pande (2009) designed a 3D
NoC architecture based on 3D mesh, 3D butterfly fat-tree (BFT), and 3D fat tree
topologies having 64 IP cores of size 2.5 mm × 2.5 mm each. They used a flit size
of 32 bits and four virtual channels each of two flits deep. The frequency of each
router is found to be 1.66 GHz in 90-nm technology after synthesis.
Some asynchronous NoCs have also been reported in the literature.
MANGO (Bjerregaard and Sparsoe 2005), a clock-less NoC, uses the 2D mesh