8
Network-on-Chip
In the many-core era, integrating large number of cores on a two-dimensional
integrated circuit (2D IC) has limited the floor planning choice. Although the
size of an individual core is reduced up to a certain level due to technology
shrinking, chip sizes may become larger for incorporating huge number of
cores on a single silicon die. After the advent of three-dimensional (3D) IC
(Davis et al. 2005) that stacks multiple layers of active silicon using special vertical interconnects, known as through-silicon vias (TSVs), the above-mentioned
problem of long interconnects can be solved. The actual benefit of 3D IC relies
on the fact that the relatively long wires (approximately in millimeters) of 2D
IC can be replaced by these TSVs whose lengths are about tens of microns.
These shorter TSVs minimize the link delay and link energy consumption significantly and at the same time more immunity to noise (Topol et al. 2006; Flic
and Bertozzi 2010). Due to increased connectivity, 3D ICs have the potential for
enhancing system performance, achieving better functionality, and producing
higher packaging density compared to their traditional 2D counterpart (Davis
et al. 2005). Combining these two emerging paradigms, NoC and 3D IC, a new
area of research, 3D NoC, has evolved (Pavlidis and Friedman 2007). In a 3D
NoC, an entire 2D NoC is divided into a number of blocks, and each block is
placed on a separate silicon layer. The 3D NoC research is still in its infancy
and needs attention of more researchers to exploit its full potential for using as
communication backbone for future many-core-based SoCs.
1.4 Existing NoC Examples
Several research groups from academia and industry have implemented NoC
to support MPSoC platform. Intel has introduced 80-core-based Teraflops
research chip (Vangal et al. 2008) where each core is placed inside a tile of
dimension 2 mm × 1.5 mm. The cores are connected in a 2D mesh topology
and support wormhole switching of 32-bit flit size with two virtual channels.
The routers have been implemented in 65-nm technology with five-stage pipelining. The operating frequency of the router has been found to be 4.27 GHz
when implemented on a chip. IBM launched Cyclops-64 (C64), a peta-flop
supercomputer, built on a multicore system-on-a-chip technology. Each C64
chip has 80 custom-designed 64-bit processor cores, which are connected in
a 3D mesh fashion (Zhang et al. 2006). The routers have been implemented
using two virtual channels to support two service classes. It uses both input
and output queuing with seven-stage pipelining and operates at 533 MHz. It
can transfer bidirectional data in parallel. Tilera Inc. has introduced a 64-corebased TILE64 processor (Wentzlaff et al. 2007). The routers are connected in an
8 × 8 2D mesh fashion and follow XY routing having a 32-bit link width with
no virtual channel. The routers are working at 1 GHz when implemented
on silicon in 90-nm technology having both input and output buffering. For