Processor
+ cache
Processor
+ cache
Processor
+ cache
Processor
+ cache
Memory
I/O
Memory
I/O
Memory
I/O
Memory
I/O
Interconnection network
Memory
I/O
Memory
I/O
Memory
I/O
Memory
I/O
Processor
+ cache
Processor
+ cache
Processor
+ cache
Processor
+ cache
2
Interconnection Networks
in Network-on-Chip
2.1 Introduction
In most modern multiprocessor system-on-chip (MPSoC) architectures,
processors and memories are combined in an integrated node. With this
arrangement, each processor can access its local memory without using the
network. Interconnection networks are also used to connect I/O devices such
as disk drives and displays as shown in Figure 2.1. To meet the performance
requirement of a specific application, network designer must work within
technology constraints to implement the topology, routing, and flow control
mechanisms of the network.
In a network topology, the nodes are connected in a different fashion such as
mesh and tree. Once a topology has been chosen, routing determines the path
through which packets will traverse to the destination. If there are multiple
Figure 2.1
Interconnection network.
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