286
Network-on-Chip
Korotkyi, I. and Lysenko, O. 2012. Application-specific network-on-chip with link
aggregation, Proceedings of the Mediterranean Conference on Embedded Computing,
IEEE, pp. 9–12.
Lai, G., Lin, X., and Lai, S. 2010. GA-based floorplan-aware topology synthesis of
application-specific network-on-chip. Proceedings of the IEEE International
Conference on Intelligent Computing and Intelligent Systems, IEEE, pp. 554–558.
Leary, G. and Chatha, K. S. 2010. A holistic approach to network-on-chip synthesis,
Proceedings of the IEEE/ACM/IFIP International Conference on Hardware/Software
Codesign and System Synthesis, IEEE, pp. 213–222.
Leary, G., Srinivasan, K., Mehta, K., and Chatha, K. S. 2009. Design of network-onchip architectures with a genetic algorithm-based technique. IEEE Transactions
on Very Large Scale Integration (VLSI) Systems, vol.17, no.5, pp. 674–687.
Li, X. and Hammami, O. 2010. Multi-objective network-on-chip synthesis with
transaction level simulation. Proceedings of the International Conference on
Microelectronics, IEEE, pp. 487–490.
Lin, S., Su, L., Haibo, S., Depeng J., and Zeng, L. 2008. Hierarchical cluster-based irregular topology customization for networks-on-chip. Proceedings of the IEEE/IFIP
International Conference on Embedded and Ubiquitous Computing, IEEE, pp. 373–377.
M’zah, A. and Hammami, O. 2011. Area/delay driven NoC synthesis. Proceedings of
the International Conference on Microelectronics (ICM), IEEE, pp. 1–6.
Morgan, A. A., Elmiligi, H., El-Kharashi, M. W., and Gebali, F. 2009. Area-aware
topology generation for application-specific networks-on-chip using network
partitioning. Proceedings of the IEEE Pacific Rim Conference on Communications,
Computers and Signal Processing, IEEE, pp. 979–984.
Morgan, A. A., Elmiligi, H., Watheq, E. M., and Gebali, F. 2008. Networks-on-Chip
topology generation techniques: Area and delay evaluation. Proceedings of the
Design and Test Workshop, IEEE, pp. 33–38.
Murali, S., Meloni, P., Angiolini, F., Atienza, D., Carta, S., Benini, L., Micheli, G. D., and
Raffo, L. 2006. Designing application-specific networks on chips with floorplan
information. Proceedings of the IEEE/ACM International Conference on ComputerAided Design Computer-Aided Design, IEEE, pp. 355–362.
Murali, S. and Micheli, G. D. 2004. Bandwidth constrained mapping of cores onto
NoC architectures. Proceedings of Design, Automation and Test in Europe Conference
and Exhibition, pp. 896–901.
Ogras, U. Y. and Marculescu, R. 2005a. Application-specific network-on-chip architecture customization via long-range link insertion. Proceedings of the IEEE/ACM
International Conference on Computer-Aided Design, IEEE, pp. 246–253.
Ogras, U. Y. and Marculescu, R. 2005b. Energy- and performance-driven NoC communication architecture synthesis using a decomposition approach. Proceedings
of the Design, Automation and Test in Europe, IEEE, pp. 352–357.
Pinto, A., Carloni, L. P., and Sangiovanni-Vincentelli, A. L. 2003. Efficient synthesis of
networks on chip, Proceedings of the International Conference on Computer Design,
IEEE, pp. 146–150.
Ravi, R., Marathe, M. V., Ravi, S. S., Ronenkarntz, D. J., and Hunt, H. B. 2001.
Approximation algorithms for degree-constrained minimum-cost network
design problems. Algorithmica, vol. 31, no. 1, pp. 58–78.
Reza K. M., Angiolin, F., Murali, S., Pullini, A., Seiculescu, C., and Benini, L. 2009.
A floorplan-aware interactive tool flow for NoC design and synthesis.
Proceedings of the IEEE International SOC Conference, IEEE, pp. 379–382.
Network-on-Chip
Korotkyi, I. and Lysenko, O. 2012. Application-specific network-on-chip with link
aggregation, Proceedings of the Mediterranean Conference on Embedded Computing,
IEEE, pp. 9–12.
Lai, G., Lin, X., and Lai, S. 2010. GA-based floorplan-aware topology synthesis of
application-specific network-on-chip. Proceedings of the IEEE International
Conference on Intelligent Computing and Intelligent Systems, IEEE, pp. 554–558.
Leary, G. and Chatha, K. S. 2010. A holistic approach to network-on-chip synthesis,
Proceedings of the IEEE/ACM/IFIP International Conference on Hardware/Software
Codesign and System Synthesis, IEEE, pp. 213–222.
Leary, G., Srinivasan, K., Mehta, K., and Chatha, K. S. 2009. Design of network-onchip architectures with a genetic algorithm-based technique. IEEE Transactions
on Very Large Scale Integration (VLSI) Systems, vol.17, no.5, pp. 674–687.
Li, X. and Hammami, O. 2010. Multi-objective network-on-chip synthesis with
transaction level simulation. Proceedings of the International Conference on
Microelectronics, IEEE, pp. 487–490.
Lin, S., Su, L., Haibo, S., Depeng J., and Zeng, L. 2008. Hierarchical cluster-based irregular topology customization for networks-on-chip. Proceedings of the IEEE/IFIP
International Conference on Embedded and Ubiquitous Computing, IEEE, pp. 373–377.
M’zah, A. and Hammami, O. 2011. Area/delay driven NoC synthesis. Proceedings of
the International Conference on Microelectronics (ICM), IEEE, pp. 1–6.
Morgan, A. A., Elmiligi, H., El-Kharashi, M. W., and Gebali, F. 2009. Area-aware
topology generation for application-specific networks-on-chip using network
partitioning. Proceedings of the IEEE Pacific Rim Conference on Communications,
Computers and Signal Processing, IEEE, pp. 979–984.
Morgan, A. A., Elmiligi, H., Watheq, E. M., and Gebali, F. 2008. Networks-on-Chip
topology generation techniques: Area and delay evaluation. Proceedings of the
Design and Test Workshop, IEEE, pp. 33–38.
Murali, S., Meloni, P., Angiolini, F., Atienza, D., Carta, S., Benini, L., Micheli, G. D., and
Raffo, L. 2006. Designing application-specific networks on chips with floorplan
information. Proceedings of the IEEE/ACM International Conference on ComputerAided Design Computer-Aided Design, IEEE, pp. 355–362.
Murali, S. and Micheli, G. D. 2004. Bandwidth constrained mapping of cores onto
NoC architectures. Proceedings of Design, Automation and Test in Europe Conference
and Exhibition, pp. 896–901.
Ogras, U. Y. and Marculescu, R. 2005a. Application-specific network-on-chip architecture customization via long-range link insertion. Proceedings of the IEEE/ACM
International Conference on Computer-Aided Design, IEEE, pp. 246–253.
Ogras, U. Y. and Marculescu, R. 2005b. Energy- and performance-driven NoC communication architecture synthesis using a decomposition approach. Proceedings
of the Design, Automation and Test in Europe, IEEE, pp. 352–357.
Pinto, A., Carloni, L. P., and Sangiovanni-Vincentelli, A. L. 2003. Efficient synthesis of
networks on chip, Proceedings of the International Conference on Computer Design,
IEEE, pp. 146–150.
Ravi, R., Marathe, M. V., Ravi, S. S., Ronenkarntz, D. J., and Hunt, H. B. 2001.
Approximation algorithms for degree-constrained minimum-cost network
design problems. Algorithmica, vol. 31, no. 1, pp. 58–78.
Reza K. M., Angiolin, F., Murali, S., Pullini, A., Seiculescu, C., and Benini, L. 2009.
A floorplan-aware interactive tool flow for NoC design and synthesis.
Proceedings of the IEEE International SOC Conference, IEEE, pp. 379–382.