287
Application-Specific Network-on-Chip Synthesis
Roy, G. D. 1978. U-statistic hierarchical clustering, Psychometrica, vol. 4, no. 1,
pp. 58–67.
Salminen, E., Kulmala, A., and Hmlinen, T. D. 2008. Survey of network-on-chip proposals, Technical Report, http://www.ocpip.org/socket/whitepapers.
Sait, S. M. and Youssef, H. 1994. VLSI Physical Design Automation: Theory and Practice.
McGraw-Hill, New York.
Sami, J. H. and Mohammad, G. M. 2006. Q8WARE: Synthesis tool for network-onchip applications. Innovations in Information Technology, pp. 1–5.
Shan, Y. and Lin, B. 2008. Application-specific network-on-chip architecture synthesis
based on set partitions and steiner trees. Proceedings of the Asia and South Pacific
Design Automation Conference, IEEE, pp. 277–282.
Soumya, J. and Chattopadhyay, S. 2013. Application-specific network-on-chip synthesis with flexible router placement, Journal of Systems Architecture, vol. 59,
pp. 361–371.
Srinivasan, K. and Chatha, K. S. 2005. SAGA: Synthesis technique for guaranteed
throughput NoC architectures. Proceedings of the Asia and South Pacific Design
Automation Conference, IEEE, pp. 489–494.
Srinivasan, K., Chatha, K. S., and Konjevod, G. 2005. An automated technique for
topology and route generation of application specific on-chip interconnection
networks. Proceedings of the IEEE/ACM International Conference on ComputerAided Design, IEEE, pp. 231–237.
Srinivasan, K., Chatha, K. S., and Konjevod, G. 2006. Linear-programming-based
techniques for synthesis of network-on-chip architectures. IEEE Transactions on
Very Large Scale Integration (VLSI) Systems, vol. 14, no. 4, pp. 407–420.
Stergiou, S., Angiolini, F., Carta, S., Raffo, L., Bertozzi, D., and Micheli, G. D.
2005. xpipes Lite: A synthesis oriented design library for networks on chips.
Proceedings of the Design, Automation and Test in Europe, IEEE, pp. 1188–1193.
Tino, A. and Khan, G. N. 2011. Multi-objective tabu search based topology generation
technique for application-specific network-on-chip architectures. Proceedings of
the Design, Automation & Test in Europe Conference & Exhibition, IEEE, pp. 1–6.
Wang, K. P., Huang, L., Zhou, C. G., and Wei, P. 2003. Particle swarm optimization
for traveling salesman problem. Proceedings of the International Conference on
Machine Learning and Cybernetics, IEEE, pp. 1583–1585.
Zhong, W., Yu, B., Song, C., Yoshimura, T., Dong, S., and Goto, S. 2011. Applicationspecific network-on-chip synthesis: Cluster generation and network component
insertion. Proceedings of the International Symposium on Quality Electronic Design,
IEEE, pp. 1–6.
Application-Specific Network-on-Chip Synthesis
Roy, G. D. 1978. U-statistic hierarchical clustering, Psychometrica, vol. 4, no. 1,
pp. 58–67.
Salminen, E., Kulmala, A., and Hmlinen, T. D. 2008. Survey of network-on-chip proposals, Technical Report, http://www.ocpip.org/socket/whitepapers.
Sait, S. M. and Youssef, H. 1994. VLSI Physical Design Automation: Theory and Practice.
McGraw-Hill, New York.
Sami, J. H. and Mohammad, G. M. 2006. Q8WARE: Synthesis tool for network-onchip applications. Innovations in Information Technology, pp. 1–5.
Shan, Y. and Lin, B. 2008. Application-specific network-on-chip architecture synthesis
based on set partitions and steiner trees. Proceedings of the Asia and South Pacific
Design Automation Conference, IEEE, pp. 277–282.
Soumya, J. and Chattopadhyay, S. 2013. Application-specific network-on-chip synthesis with flexible router placement, Journal of Systems Architecture, vol. 59,
pp. 361–371.
Srinivasan, K. and Chatha, K. S. 2005. SAGA: Synthesis technique for guaranteed
throughput NoC architectures. Proceedings of the Asia and South Pacific Design
Automation Conference, IEEE, pp. 489–494.
Srinivasan, K., Chatha, K. S., and Konjevod, G. 2005. An automated technique for
topology and route generation of application specific on-chip interconnection
networks. Proceedings of the IEEE/ACM International Conference on ComputerAided Design, IEEE, pp. 231–237.
Srinivasan, K., Chatha, K. S., and Konjevod, G. 2006. Linear-programming-based
techniques for synthesis of network-on-chip architectures. IEEE Transactions on
Very Large Scale Integration (VLSI) Systems, vol. 14, no. 4, pp. 407–420.
Stergiou, S., Angiolini, F., Carta, S., Raffo, L., Bertozzi, D., and Micheli, G. D.
2005. xpipes Lite: A synthesis oriented design library for networks on chips.
Proceedings of the Design, Automation and Test in Europe, IEEE, pp. 1188–1193.
Tino, A. and Khan, G. N. 2011. Multi-objective tabu search based topology generation
technique for application-specific network-on-chip architectures. Proceedings of
the Design, Automation & Test in Europe Conference & Exhibition, IEEE, pp. 1–6.
Wang, K. P., Huang, L., Zhou, C. G., and Wei, P. 2003. Particle swarm optimization
for traveling salesman problem. Proceedings of the International Conference on
Machine Learning and Cybernetics, IEEE, pp. 1583–1585.
Zhong, W., Yu, B., Song, C., Yoshimura, T., Dong, S., and Goto, S. 2011. Applicationspecific network-on-chip synthesis: Cluster generation and network component
insertion. Proceedings of the International Symposium on Quality Electronic Design,
IEEE, pp. 1–6.