285
Application-Specific Network-on-Chip Synthesis
Ascia, G., Catania, V., and Palesi, M. 2004. Multi-objective mapping for mesh-based
noc architectures. Proceedings of the International Conference on Hardware/Software
Codesign and System Synthesis, IEEE, pp. 182–187.
Bei, Y., Dong, S., Chen, S., and Goto, S. 2010. Floorplanning and topology generation
for application-specific network-on-chip. Proceedings of the Asia and South Pacific
Design Automation Conference, IEEE, pp. 535–540.
Benini, L. 2006. Application specific NoC design. Proceedings of Design, Automation and
Test in Europe Conference and Exhibition, IEEE, pp. 1–5.
Bertozzi, D., Jalabert, A., Murali, S., Tamhankar, R., Stergiou, S., Benini, L., and
Micheli, G. D. 2005. NoC synthesis flow for customized domain specific multiprocessor systems-on-chip, IEEE Transactions on Parallel and Distributed Systems,
vol. 16, no. 2, pp. 113–129.
Binjie, S., Shan, Z., Ma, Y., Xu, N., and Wang, Y. 2011. Tree-based partitioning approach
for network-on-chip synthesis. Proceedings of the International Conference on
Computer-Aided Design and Computer Graphics, IEEE, pp. 465–470.
Chan, J. and Parameswaran, S. 2008. NoCOUT: NoC topology generation with mixed
packet-switched and point-to-point networks. Proceedings of the Asia and South Pacific
Design Automation Conference Design Automation Conference, IEEE, pp. 265–270.
Choudhary, N., Gaur, M. S., Laxmi, V., and Singh, V. 2010. Energy aware design methodologies for application specific NoC, Proceedings of the NORCHIP, IEEE, pp. 1–4.
Choudhary, N., Gaur, M. S., Laxmi, V., and Singh, V. 2011. GA based congestion
aware topology generation for application specific NoC, Proceedings of the IEEE
International Symposium on Electronic Design, Test and Application, IEEE, pp. 93–98.
Dumitriu, V. and Khan, G. N. 2009. Throughput-oriented NoC topology generation
and analysis for high performance SoCs. IEEE Transactions on Very Large Scale
Integration (VLSI) Systems, vol. 17, no. 10, pp. 1433–1446.
Filippopoulos, I., Anagnostopoulos, I., Bartzas, A., Soudris, D., and Economakos, G.
2010. Systematic exploration of energy-efficient application-specific networkon-chip architectures, Proceedings of the IEEE Computer Society Annual Symposium
on VLSI, IEEE, pp. 133–138.
Garey, M. R. and Johnson, D. S. 1979. Computers and Intractability: A Guide to the Theory
of NP-Completeness. Sanfrancisco, CA: Freeman.
Ho, R., Mai, K. W., and Horowitz, M. A. 2001. The future of wires. Proceedings of the
IEEE, vol. 89, no. 4, pp. 490–504.
Hu, Y., Chen, H., Zhu, Y., Chien, A. A., and Cheng, C. K. 2005. Physical synthesis of
energy-efficient networks-on-chip through topology exploration and wire style
optimization. Proceedings of the IEEE International Conference on Computer Design:
VLSI in Computers and Processors, IEEE, pp. 111–118.
Jalabert, A., Murali, S., Benini, L., and Micheli, G. D. 2004. ×pipesCompiler: A tool
for instantiating application specific networks on chip. Proceedings of the Design,
Automation and Test in Europe Conference and Exhibition, IEEE, pp. 884–889.
Kennedy, J. and Eberhart, R. 1995. Particle swarm optimization. Proceedings of the IEEE
International Conference on Neural Networks, vol. 4, IEEE, pp. 1942–1948.
Khan, G. N. and Tino, A. 2012. Synthesis of NoC interconnects for custom MPSoC
architectures. Proceedings of the IEEE/ACM International Symposium on Networks
on Chip, IEEE, pp. 75–82.
Kwon, S., Pasricha, S., and Cho, J. 2011. POSEIDON: Aframework for application-specific
network-on-chip synthesis for heterogeneous chip multiprocessors. Proceedings of
the International Symposium on Quality Electronic Design, IEEE, pp. 1–7.
Application-Specific Network-on-Chip Synthesis
Ascia, G., Catania, V., and Palesi, M. 2004. Multi-objective mapping for mesh-based
noc architectures. Proceedings of the International Conference on Hardware/Software
Codesign and System Synthesis, IEEE, pp. 182–187.
Bei, Y., Dong, S., Chen, S., and Goto, S. 2010. Floorplanning and topology generation
for application-specific network-on-chip. Proceedings of the Asia and South Pacific
Design Automation Conference, IEEE, pp. 535–540.
Benini, L. 2006. Application specific NoC design. Proceedings of Design, Automation and
Test in Europe Conference and Exhibition, IEEE, pp. 1–5.
Bertozzi, D., Jalabert, A., Murali, S., Tamhankar, R., Stergiou, S., Benini, L., and
Micheli, G. D. 2005. NoC synthesis flow for customized domain specific multiprocessor systems-on-chip, IEEE Transactions on Parallel and Distributed Systems,
vol. 16, no. 2, pp. 113–129.
Binjie, S., Shan, Z., Ma, Y., Xu, N., and Wang, Y. 2011. Tree-based partitioning approach
for network-on-chip synthesis. Proceedings of the International Conference on
Computer-Aided Design and Computer Graphics, IEEE, pp. 465–470.
Chan, J. and Parameswaran, S. 2008. NoCOUT: NoC topology generation with mixed
packet-switched and point-to-point networks. Proceedings of the Asia and South Pacific
Design Automation Conference Design Automation Conference, IEEE, pp. 265–270.
Choudhary, N., Gaur, M. S., Laxmi, V., and Singh, V. 2010. Energy aware design methodologies for application specific NoC, Proceedings of the NORCHIP, IEEE, pp. 1–4.
Choudhary, N., Gaur, M. S., Laxmi, V., and Singh, V. 2011. GA based congestion
aware topology generation for application specific NoC, Proceedings of the IEEE
International Symposium on Electronic Design, Test and Application, IEEE, pp. 93–98.
Dumitriu, V. and Khan, G. N. 2009. Throughput-oriented NoC topology generation
and analysis for high performance SoCs. IEEE Transactions on Very Large Scale
Integration (VLSI) Systems, vol. 17, no. 10, pp. 1433–1446.
Filippopoulos, I., Anagnostopoulos, I., Bartzas, A., Soudris, D., and Economakos, G.
2010. Systematic exploration of energy-efficient application-specific networkon-chip architectures, Proceedings of the IEEE Computer Society Annual Symposium
on VLSI, IEEE, pp. 133–138.
Garey, M. R. and Johnson, D. S. 1979. Computers and Intractability: A Guide to the Theory
of NP-Completeness. Sanfrancisco, CA: Freeman.
Ho, R., Mai, K. W., and Horowitz, M. A. 2001. The future of wires. Proceedings of the
IEEE, vol. 89, no. 4, pp. 490–504.
Hu, Y., Chen, H., Zhu, Y., Chien, A. A., and Cheng, C. K. 2005. Physical synthesis of
energy-efficient networks-on-chip through topology exploration and wire style
optimization. Proceedings of the IEEE International Conference on Computer Design:
VLSI in Computers and Processors, IEEE, pp. 111–118.
Jalabert, A., Murali, S., Benini, L., and Micheli, G. D. 2004. ×pipesCompiler: A tool
for instantiating application specific networks on chip. Proceedings of the Design,
Automation and Test in Europe Conference and Exhibition, IEEE, pp. 884–889.
Kennedy, J. and Eberhart, R. 1995. Particle swarm optimization. Proceedings of the IEEE
International Conference on Neural Networks, vol. 4, IEEE, pp. 1942–1948.
Khan, G. N. and Tino, A. 2012. Synthesis of NoC interconnects for custom MPSoC
architectures. Proceedings of the IEEE/ACM International Symposium on Networks
on Chip, IEEE, pp. 75–82.
Kwon, S., Pasricha, S., and Cho, J. 2011. POSEIDON: Aframework for application-specific
network-on-chip synthesis for heterogeneous chip multiprocessors. Proceedings of
the International Symposium on Quality Electronic Design, IEEE, pp. 1–7.