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Network-on-Chip
9.4 System-Level Floorplanning
This section discusses a mixed integer linear programming (MILP)-based
approach to solve the NoC-centric floorplanning problem (Srinivasan et al.
2006). Since the interconnection architecture is not known at this stage,
the interconnect power can be approximated in terms of communication
via point-to-point links between communicating cores. Another important factor is to satisfy the latency constraints for communication between
cores. It may be difficult to satisfy the latency constraints for cores placed
far away. Apart from power and latency, we can also minimize the overall layout area. Hence, the minimization goal is a linear combination of
power–latency function and the area of the layout, as shown in the following equation:
⎡
⎤
ω( )
e
α × ∑ dist( , )× Ψ l ×
β [X
⎢
u v
2
⎥ + × max + Y max ]
(9.1)
⎢ ( )
σ ( )
e ⎥
⎣ ∀e u v
, ∈E
⎦
where:
dist(u,v) is the distance between cores u and v
α and β are constants
X max and Y max represent the boundaries in X and Y directions respectively
Rest of the variables are as defined in Section 9.2
The objective function puts more emphasis on latency constraint compared
to the bandwidth. The values of α and β determine the relative weight given
to power minimization compared to area minimization.
9.4.1 Variables
9.4.1.1 Independent Variables
For each core v i ∊ V, let (X i,min , Y i,min ) denote the lower left coordinate of the
placed core.
9.4.1.2 Dependent Variables
• For each core v i ∊ V, let (X i,max , Y i,max ) denote the upper right coordinate
of the placed core. Hence,
X i,max = X i,min +W i ; Y i,max = Y i,min + H i
• For each pair of cores v i , v j  ∊ V, let DX i,j and DY i,j represent the differences between the X and Y coordinates of the top right corner of the
placed cores. Thus,