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Application-Specific Network-on-Chip Synthesis
In the work of Srinivasan et al. (2005), a slicing tree-based floorplanner
is used during the topology design process. This work assumes that the
switches to be located at a corner of the cores and the network components
are not considered in the floorplanning process. NoC topology generation algorithms were presented by Srinivasan et al. (2006) based on slicing
structures where switch locations are restricted to the corners of the cores.
A two-step topology generation procedure was proposed by Murali et al.
(2006) using a min-cut partitioner to cluster highly communicating cores
on the same switch and a path allocation algorithm to connect clusters
together to minimize power consumption. An iterative refinement strategy to generate an optimized NoC topology that supports both packetswitched network and point-to-point communications was presented by
Chan et al. (2008). This assumes the network interfaces for the processing
cores to be located on the corners, whereas the router nodes are in the
center. A partition-driven floorplanning algorithm that uses a heuristic to
insert switches and an algorithm for inserting NIs, limited to mosaic type
of floorplans was proposed by Bei et al. (2010). Two heuristic algorithms
were proposed by Shan and Lin (2008) to examine different set partitions.
Partitioning is carried out based on the communication flow and a physical network topology has to be generated for each partition. A three-stage
synthesis approach was presented by Zhong et al. (2011) that integrates
communication requirements, physical information among cores, and
partitioning into the floorplanning phase to explore the optimal switch
number for clustering of cores with minimized link and switch power
consumption. A complete synthesis flow was illustrated by Bertozzi et al.
(2005) for customized NoC architectures. It partitions the flow into three
major steps: topology mapping, selection, and generation. Tools, such as
SUNMAP and Xpipes Compiler, are provided for their automatic execution. Thermal- and nonthermal-aware ASNoC synthesis frameworks that
combine multiple algorithms and heuristics to efficiently explore the solution space were presented by Kwon et al. (2011). This work describes both
thermal- and nonthermal-aware approaches for router placement. Both the
techniques assume that switches can only be placed at the interconnection
of cores in the floorplan. A topology generation method was presented
by Khan and Tino (2012) by employing analytical models and simulation tools to design low-power, high-performance custom NoCs. Hu et al.
(2005) has presented a work on energy-efficient NoC synthesis through
topology exploration and wire optimization. The above works generate
floorplan as part of the synthesis process.
In the following section, we will look into a few strategies to solve the
ASNoC synthesis problem. The first one addresses system-level floorplanning to minimize NoC power consumption subject to layout constraints.
This will be followed by discussion on custom topology and route generation. We will also discuss on a scheme to intelligently put routers in a given
NoC floorplan to optimize communication cost and energy consumed.