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Network-on-Chip
hardware reusability constraints. A genetic algorithm (GA)-based technique
was presented by Srinivasan and Chatha (2005) for synthesis of custom NoC
architectures that support guaranteed throughput traffic. The energy consumption of NoC is optimized by minimizing the cumulative traffic flowing
through the ports of all routers. The total area consumption is minimized
by reducing the total number of routers used. A methodology for generating energy-efficient application-specific architectures was presented by
Filippopoulos et al. (2010). It uses application partitioning to reduce processing element dependencies. Topology exploration and buffer sizing techniques
are utilized to generate custom topology with reduced power consumption.
A NoC topology generation and analysis method was presented by Dumitriu
and Khan (2009) that addresses throughput requirements by considering
the latency present in the system. An irregular application-specific topology generation algorithm was presented by Ar et al. (2009) to reduce power
consumption. It clusters the given application, based on the communication
characteristics, and then constructs the topology by connecting clusters to
each other, one by one. A partitioning approach based on trees has been
presented in Binijie et al. (2011) for NoC synthesis. Genetic algorithm-based
techniques have been proposed in Choudhary et al. (2010, 2011) for application specific NoC design.
Next, we look into the floorplan-aware methodologies. Alabei (2010)
has proposed a custom NoC synthesis procedure that uses B*-tree for
floorplan representation. A multiobjective mathematical model for NoC
synthesis has been suggested in Abderazek et al. (2007). A custom NoC
instantiation tool Xpipes Compiler was presented by Jalabert et al. (2004),
which is based on the inputs as specified by the designer. A floorplanaware tool was presented by Reza et al. (2009) for NoC design and synthesis, integrated with a graphical user interface for interacting among
abstract traffic flow specification, topology synthesis, and floorplanning.
A GA-based technique was presented by Leary et al. (2009) for ASNoC
design with an objective of minimizing the power consumption. This
work assumes the routers to be at the corners of the cores. A branchand-bound algorithm was proposed by Ogras and Marculescu (2005b)
for customized communication architecture synthesis. It uses the core
coordinates from the floorplan. A GA-based topology synthesis method
was proposed by Lai et al. (2010) to minimize power consumption by taking floorplan information. This work also assumes the routers to be at
the corners of the cores. A multiobjective approach to topology design
based on Tabu search technique was presented by Tino and Khan (2011) to
meet power and performance requirements of an application. A synthesisoriented design flow, xpipes lite, was presented by Stergiou et al. (2005)
for the generation of synthesizable simultaneous models for ASNoCs. In
the work of Ahoen et al. (2004), a physical floorplan is used during topology design to reduce power consumption on wires. However, the area
and power consumption of the switches are not taken into consideration.