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designed simultaneously. The other option is to start with a given floorplan
of the IP cores and then insert routers at appropriate positions within the
floorplan so that the interconnect network gets synthesized.
9.3 Literature Survey
A survey of ASNoC design techniques was presented by Ascia et al. (2004).
It enumerates the advantages of custom topologies over standard ones for
ASNoC. While some of the design techniques attempt to modify a regular
topology to take into consideration the variation in core sizes and communication pattern, others try to synthesize the most suited topology. A performance-aware design methodology of inserting long-range interconnects on
top of a regular mesh-based network for synthesis of application-specific
architectures was presented by Ogras and Marculescu (2005a). Challenges in
application specific NoC design have been surveyed in Benini (2006). In the
following, the major ASNoC synthesis works will be reviewed.
First, we will look into the strategies that do not consider the floorplan of
the NoC. A holistic approach for application-specific NoC synthesis has been
presented in Leary and Chatha (2010). It results in solution with minimum
dynamic power, at most twice the number of routers and leakage, compared
to the optimal solution. Average communication latency and jitter are also
low. A multiobjective NoC synthesis approach has been presented in Li
and Harmanani (2010). A heuristic was proposed by Pinto et  al. (2003) for
a constraint-driven communication synthesis of on-chip networks. A quadratic programming-based approach along with a clustering algorithm was
proposed for this purpose. However, no floorplan information is utilized
during the topology generation process. A method to reduce hardware cost
of NoC via link aggregation was presented by Korotkyi et al. (2012). It creates
ASNoC with nonuniform distribution of physical links in logical connections, depending on the amount of network traffic that is passed through
them. A network partitioning technique based on Fiduccia–Mattheyses (FM)
partitioning algorithm was proposed in the work of Morgan et al. (2009) to
reduce the area cost. A linear programming based technique was proposed
in the work of M’zah and Hammami (2011) to generate an area-optimized
NoC architecture constrained to propagation delay time and bandwidth
requirements. Different topology generation techniques were analyzed and
compared in the work of Morgan et al. (2008) with respect to area and average delay. This work analyzed network partitioning techniques and longrange generation techniques, thus determining the best scheme to be used
for NoC topology generation. A tool, Q8WARE, was presented by Sami and
Mohammad (2006), which is a small-scale version of Application Specific
Integrated Circuit assembly line. It  deals with synthesis of ASNoC with