WPI[0:2]
Scan chain
Scan chain
d[0]
d[1]
d[2]
d[3]
d[4]
q[2]
q[1]
q[0]
Core
CLK SC
WBY
WIR
WSC
Wrapper
WPO[0:2]
d[0]
q[0]
d[1]

d[2]

q[1]
d[3]

d[4]

q[2]
CLK

SC

WSO
WSI
247
Testing of Network-on-Chip Architectures
Figure 8.6
1500 Wrapper. CLK, functional clock; d, functional inputs; q, Functional outputs; SC, Scan
Enable Control; WIR, Wrapper Instruction Register; WBY, Wrapper Wide Bypass; WPI,
Wrapper Parallel Input; WPO, Wrapper Parallel Output; WSI, Wrapper Serial Input; WSC,
Wrapper Scan Control; WSO, Wrapper Serial Output.
assign n + m + sc wrapper scan chain elements to k′ ≤ k, such that max{s i , s o }
is minimized, where s i and s o are the lengths of the longest wrapper scan-in
and scan-out chains, respectively. Also, try to minimize k′.
The wrapper design algorithm proposed in the work of Iyengar and
Chakrabarty (2002) uses an approximation algorithm based on the best fit
decreasing (BFD) heuristics (Garey and Johnson 1979). The algorithm has
three main parts: (1) partition the internal scan chains among a minimal
number of wrapper scan chains to minimize the longest wrapper scan chain
length, (2) assign the functional inputs to the wrapper chains created in
part (1), and (3) assign the functional outputs to the wrapper scan chains
created so far. To solve the problem, first the internal scan chains are sorted in
descending order of their length. Each internal scan chain is then attached to
a wrapper scan chain, whose length after this assignment is closest to, but not
exceeding, the current maximum wrapper scan chain length. In other words,