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Testing of Network-on-Chip Architectures
8.3 Testing Cores
Once the NoC fabric has been tested and found okay, the cores of the NoC are
tested. The network resources (switches and links) are used to transport the
test patterns. The cores embedded deep inside the chip are difficult to access,
whereas the cores near the periphery of the chip may be direct accessibility
from the chip input/output pins. As a result, the input/output channels of the
automated test equipment (ATE) can be connected to the cores in the periphery. These cores are conveniently called I/O ports for testing. For a core deep
inside the NoC, its test patterns can be transported to a core acting as input
port. From this core, the patterns are transferred over the network to the
core under test. Similarly, the responses from the core under test are transferred to the output core for subsequent delivery to the ATE for analysis.
Figure 8.5 shows a NoC with two input cores and two output cores. A pair of
input/output cores can be connected to an ATE channel for testing purpose.
Since in Figure 8.5 there are two I/O ports, two cores can be tested in parallel,
provided that the resources (switches and links) needed are not conflicting.
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Input
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Figure 8.5
NoC with input/output cores for testing and two routing paths.