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Network-on-Chip
The overall TAM structure is divided into a number of buses to carry out the
test in parallel.
However, in a NoC environment, usage of extra TAM is not advisable. The
chip itself contains a full network for transport of test packets through it to
the individual cores. Hence, it is imperative to use the existing communication backbone for carrying the test patterns from the test equipment connected to some pins of the chip to the individual cores and to transfer the
responses from the cores to the test equipment for analysis. The two main
issues in NoC testing are as follows:
1. Efficient testing of NoC communication fabric: In a NoC, a significant
portion of the chip is occupied by the routers and links constituting the NoC fabric. In the absence of direct signal communication
between the cores, the success of message-based communication
between them is fully dependent on the correct functioning of the
network resources. The fabric, in turn, consists of two different types
of components—the routers and the links. The routers, apart from
having the logic circuitry, also possess the first-in first-out (FIFO)
buffers. Hence, testing the communication fabric is a difficult task
as it necessitates different fault models for the components, such as
memory fault models for the FIFO, logic fault models for the router
circuitry, and link fault models for the links.
2. Testing of functional cores: In this case, the test patterns are provided by
the core vendors. The challenge is to apply these patterns to the cores.
Once the network infrastructure is tested to be okay, it is utilized to
transport the test patterns and responses through the network.
8.2 Testing Communication Fabric
Correctness of communication fabric is the first thing to be ensured to
guarantee the correct operation of the NoC. Test strategies for the fabric
must perform the following two operations (Pande et al. 2005): testing of
switch blocks and testing of interswitch wire segments. Grecu et al. (2007)
suggested a comprehensive framework to test both these components
using suitable fault models and testing mechanisms. The scheme has two
interesting features. First, the two tests are integrated together so that the
portion of the NoC determined to be correct can be utilized to test successive portions and establish their correctness. This recursive formulation
helps in arriving at an elegant solution to the test transportation problem.
Second, the NoC infrastructure is exploited successfully to introduce parallelism in the test session. This reduces the overall test time of the NoC
significantly.