8
Testing of Network-on-Chip Architectures

8.1 Introduction
Testing network-on-chip (NoC) architectures is very challenging. In fact, the
problem is difficult for any system-on-chip (SoC) design paradigm. In SoC,
the intellectual property (IP) cores are integrated into a system design. A SoC
integrator does not possess the detailed knowledge about the implementation of individual cores in the system. The netlist-level description, required
for running a test generation tool, is generally not provided by the core vendors due to IP rights. The layout-level description of the cores provided by
the vendors cannot act as input for the test generation process. Hence, the
system integrator has to depend upon the test sets provided by the core
vendors. However, core vendors, in the absence of knowledge about the
final integrated SoC platform, cannot generate a very compact test set for
their core. The core vendors do provide a test set that can ensure the correctness of only the core, not the whole integrated system. The test set provided by the core vendor needs to be applied to the input of the core and
the responses are to be observed. This poses a challenge as the input–output
lines of the cores, deeply embedded inside the chip, are not directly accessible from the system pins. In SoC platforms, the problem is often resolved
by having dedicated test access mechanism (TAM) for the chip. The TAM is
accessible from the input/output pins of the chip. The individual cores can
be accessed via this access mechanism. Several different access mechanisms
have been proposed; however, the most elegant solution is to have one or
more dedicated bus(es) for the test access. In test mode, the test signals carried by the TAM lines are applied to the core, instead of functional inputs.
Similarly, the responses from the core, instead of being applied on other
cores, are transferred to the chip output through the TAM for observation.
This solves the access problem. However, in the absence of system-level test
patterns for the entire chip, the core-level testing has to be done exhaustively. This requires application of all the test patterns for individual cores.
This leads to a huge test time for a moderate to complex SoC. Hence, test
time reduction is another important challenge. The reduction in test time is
often achieved via test parallelism—having multiple parallel test sessions.
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