234
Network-on-Chip
Sprachmann, M. 2001. Automatic generation of parallel CRC circuits. IEEE Design and
Test of Computers, vol. 18, no. 3, pp. 108–114.
Sridhara, S. R. and Shanbhag, N. R. 2005. Coding for system-on-chip networks:
A unified framework. IEEE Transactions on Very Large Scale Integration (VLSI)
Systems, vol. 13, no. 6, pp. 655–667.
Sridhara, S. R. and Shanbhag, N. R. 2007. Coding for reliable on-chip buses: A class of
fundamental bounds and practical codes. IEEE Transactions on CAD of Integrated
Circuits and Systems, vol. 26, no. 5, pp. 977–982.
Valinataj, M., Mohammadi, S., Safari, S., and Plosila, J. 2009. A link failure aware routing algorithm for networks-on-chip in nano technologies. Proceedings of IEEE
Conference on Nanotechnology, July 26–30, Genoa, Italy, IEEE, pp. 687–690.
Wang, L. T., Wu, C. W., and Wen, X. 2006. VLSI Test Principles and Architectures. Morgan
Kaufmann Publisher. San Francisco, CA.
Wu, J. 2003. A fault-tolerant and deadlock-free routing protocol in 2D meshes
based on odd-even turn model. IEEE Transactions on Computers, vol. 52, no. 9,
pp. 1154–1169.
Zhang, M., Mitra, S., Mak, T. M., Seifert, N., Wang, N. J., Shi, Q., Kim, K. S., Shanbhag,
N. R., and Patel, S. J. 2006. Sequential element design with built-in soft error
resilience. IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
vol. 14, no. 12, pp. 1368–1378.
Zimmer, H. and Jantsch, A. 2003. A fault model notation and error-control scheme
for switch-to-switch buses in a network-on-chip. Proceedings of the International
Conference on Hardware/Software Codesign and System Synthesis, October 1–3,
Newport Beach, CA, IEEE, pp. 188–193.
Network-on-Chip
Sprachmann, M. 2001. Automatic generation of parallel CRC circuits. IEEE Design and
Test of Computers, vol. 18, no. 3, pp. 108–114.
Sridhara, S. R. and Shanbhag, N. R. 2005. Coding for system-on-chip networks:
A unified framework. IEEE Transactions on Very Large Scale Integration (VLSI)
Systems, vol. 13, no. 6, pp. 655–667.
Sridhara, S. R. and Shanbhag, N. R. 2007. Coding for reliable on-chip buses: A class of
fundamental bounds and practical codes. IEEE Transactions on CAD of Integrated
Circuits and Systems, vol. 26, no. 5, pp. 977–982.
Valinataj, M., Mohammadi, S., Safari, S., and Plosila, J. 2009. A link failure aware routing algorithm for networks-on-chip in nano technologies. Proceedings of IEEE
Conference on Nanotechnology, July 26–30, Genoa, Italy, IEEE, pp. 687–690.
Wang, L. T., Wu, C. W., and Wen, X. 2006. VLSI Test Principles and Architectures. Morgan
Kaufmann Publisher. San Francisco, CA.
Wu, J. 2003. A fault-tolerant and deadlock-free routing protocol in 2D meshes
based on odd-even turn model. IEEE Transactions on Computers, vol. 52, no. 9,
pp. 1154–1169.
Zhang, M., Mitra, S., Mak, T. M., Seifert, N., Wang, N. J., Shi, Q., Kim, K. S., Shanbhag,
N. R., and Patel, S. J. 2006. Sequential element design with built-in soft error
resilience. IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
vol. 14, no. 12, pp. 1368–1378.
Zimmer, H. and Jantsch, A. 2003. A fault model notation and error-control scheme
for switch-to-switch buses in a network-on-chip. Proceedings of the International
Conference on Hardware/Software Codesign and System Synthesis, October 1–3,
Newport Beach, CA, IEEE, pp. 188–193.