233
Signal Integrity and Reliability of Network-on-Chip
Linder, D. H. and Harden, J. C. 1991. An adaptive and fault-tolerant wormhole routing
strategies for k-ary n-cubes. IEEE Transactions on Computer, vol. 40, no. 1, pp. 2–12.
Mitra, S., Zhang, M., Mak, T. M., Seifert, N., Zia, V., and Kim, K. S. 2005. Logic soft
errors: A major barrier to robust platform design. Proceedings of International Test
Conference, November 8, Austin, TX, IEEE, pp. 687–696.
Mitra, S., Zhang, M., Seifert, N., Mak, T. M., and Kim, K. S. 2006a. Soft error resilient
system design through error correction. IFIP International Conference on VLSI,
October 16–18, Nice, France, IEEE, pp. 332–337.
Mitra, S., Zhang, M., Waqas, S., Seifert, N., Gill, B., and Kim, K. S. 2006b. Combinational
logic soft error correction. Proceedings of IEEE International Test Conference,
pp. 29.2.1–29.2.9, October, Santa Clara, CA, IEEE.
Murali, S., Theocharides, T., Vijaykrishnan, N., Irwin, M. J., Benini, L., and Micheli, G. D.
2005. Analysis of error recovery schemes for Networks on Chips. Proceedings of
IEEE Design and Test of Computers, pp. 434–442, September–October, IEEE.
Nazarian, S., Pedram, M., and Tuncer, E. 2005. An empirical study of crosstalk in
VDSM technologies. Proceedings of ACM Great Lakes symposium on VLSI, April
17–19, New York, NY, ACM, pp. 317–322.
Nguyen, H. T. and Yagil, Y. 2003. A systematic approach to SER estimation and
solutions. Proceedings of IEEE International Reliability Physics Symposium,
pp. 60–70.
Pande, P. P., Ganguly, A., Feero, B., Belzer, B., and Grecu, C. 2006a. Design of low
power & reliable networks on chip through joint crosstalk avoidance and forward
error correction coding. Proceedings of IEEE International Symposium on Defect and
Fault-Tolerance in VLSI Systems, October 2006, Arlington, VA, IEEE, pp. 466–476.
Pande, P. P., Zhu, H., Ganguly, A., and Grecu, C. 2006b. Energy reduction through
crosstalk avoidance coding in NoC paradigm. Proceedings of EUROMICRO
Conference on Digital System Design, August 30–September 1, Dubrovnik, IEEE,
pp. 689–695.
Park, D., Nicopoulos, C. A., Kim, J., Vijaykrishnan, N., and Das, C. R. 2006. Exploring
fault-tolerant network-on-chip architectures. Proceedings of International Conference
on Dependable Systems and Networks, June 25–28, Philadelphia, PA, IEEE, pp. 93–102.
Patel, K. N. and Markov, I. L. 2003. Error-correction and crosstalk avoidance in DSM
busses. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Special
Issue for System Level Interconnect Prediction, vol. 12, no. 10, pp. 1–5.
Patooghy, A. and Miremadi, S. G. 2009. XYX: A power & performance efficient faulttolerant routing algorithm for network on chip. Proceedings of Parallel, Distributed,
and Network-based Processing, February 18–20, Weimer, IEEE, pp. 245–251.
Pei, T. B. and Zukowski, C. 1992. High-speed parallel CRC circuits in VLSI. IEEE
Transactions on Communications, vol. 40, no. 4, pp. 653–657.
Perez, A. 1983. Byte-wise CRC Calculation. IEEE Micro, vol. 3, no. 3, pp. 40–50.
Pullini, A., Angiolini, F., Bertozzi, D., and Benini, L. 2005. Fault tolerance overhead
in network-on-chip flow control schemes. Proceedings of Integrated Circuits and
Systems Design, September 4–7, Florianópolis, Brazil, IEEE, pp. 224–229.
Rossi, D., Metra, C., Nieuwland, A. K., and Katoch, A. 2005. New ECC for crosstalk impact minimization. IEEE Design and Test of Computers, vol. 22, no. 4,
pp. 340–348.
Shieh, M. D., Sheu, M. H., Chen, C. H., and Lo, H. F. 2001. A systematic approach
for parallel CRC computations. Journal of Information Science and Engineering,
vol. 17, pp. 445–461.