232
Network-on-Chip
Chen, K. H. and Chiu, G. M. 1998. Fault-tolerant routing algorithm for meshes without using virtual channels. Journal of Information Science and Engineering, vol. 14,
pp. 765–783.
Chen, W., Gupta, S. K., and Breuer, M. A. 1997. Analytic models for crosstalk delay
and pulse analysis under non-ideal inputs. Proceedings of International Test
Conference, November 1–6, Washington, DC, IEEE, pp. 809–818.
Cuviello, M., Dey, S., Bai, X., and Zhao, Y. 1999. Fault modeling and simulation for crosstalk
in system-on-chip interconnects. Proceedings of IEEE/ACM International Conference on
Computer Aided Design, November 7–11, San Jose, CA, IEEE, pp. 297–303.
Dally, W. J. and Poulton, J. H. 1998. Digital Systems Engineering. Cambridge University
Press, Cambridge, UK.
Dally, W. J. and Towles, B. 2004. Principles and Practices of Interconnection Networks.
Morgan Kaufmann Publishers, San Francisco, CA.
Fick, D., Orio, A. D., Chen, G., Bertacco, V., Sylvester, D., and Blaauw, D. 2009.
A highly resilient routing algorithm for fault-tolerant NoCs. Proceedings of
Design, Automation and Test in Europe Conference, April 20–24, Nice, France, IEEE,
pp. 21–26.
Fukushima, Y., Fukushi, M., and Horiguchi, S. 2009. Fault-tolerant routing algorithm
for network on chip without virtual channels. Proceedings of IEEE International
Symposium on Defect and Fault Tolerance in VLSI Systems, October 7–9, Chicago,
IL, IEEE, pp. 313–321.
Ganguly, A., Pande, P. P., Belzer, B. and Grecu, C. 2007. Addressing signal integrity in
networks on chip interconnects through crosstalk-aware double error correction
coding. Proceedings of IEEE Computer Society Annual Symposium on VLSI, March
9–11, Porto Alegre, Brazil, IEEE, pp. 317–324.
Glass, C. J. and Ni, L. 1996. Fault-tolerant wormhole routing in meshes without virtual channels. IEEE Transaction on Parallel and Distributed Systems, vol. 7, no. 6,
pp. 620–635.
Hedge, R. and Shanbhag, N. R. 2000. Toward achieving energy efficiency in presence
of deep submicron noise. IEEE Transactions on Very Large Scale Integration (VLSI)
Systems, vol. 8, no. 4, pp. 379–391.
Huang, P. T., Fang, W. L., Wang, Y. L. and Hwang, W. 2008. Low power and reliable
interconnection with self-corrected green coding scheme for network-on-chip.
Proceedings of ACM/IEEE International Symposium on Networks-on-Chip, April
7–10, Newcastle upon Tyne, IEEE, pp. 77–83.
Ismail, Y. I., Friedman, E. G., and Neves, J. L. 1998. Figures of merit to characterize the
importance of on-chip inductance. Proceedings of Design Automation Conference,
June 15–19, San Francisco, CA, IEEE, pp. 560–565.
Joshi, S. M., Dubey, P. K., and Kaplan, M. A. 2000. A new parallel algorithm for
CRC generation. IEEE International Conference on Communication, June 18–22,
New Orleans, LA, IEEE, pp. 1764–1768.
Kumar, S. V., Kim, C. H., and Sapatnekar, S. S. 2006. An analytical model for negative
bias temperature instability. Proceedings of IEEE/ACM International Conference on
Computer Aided Design, pp. 493–496.
Lee, S. J., Lee, K., and Yoo, H. J. 2005. Analysis and implementation of practical,
cost-effective networks on chips. IEEE Design & Test Computers, vol. 22, no. 5,
pp. 422–433.
Lin, S. and Costello, D. J. 1983. Error Control Coding: Fundamentals and Applications.
Prentice Hall, New Jersey.
Network-on-Chip
Chen, K. H. and Chiu, G. M. 1998. Fault-tolerant routing algorithm for meshes without using virtual channels. Journal of Information Science and Engineering, vol. 14,
pp. 765–783.
Chen, W., Gupta, S. K., and Breuer, M. A. 1997. Analytic models for crosstalk delay
and pulse analysis under non-ideal inputs. Proceedings of International Test
Conference, November 1–6, Washington, DC, IEEE, pp. 809–818.
Cuviello, M., Dey, S., Bai, X., and Zhao, Y. 1999. Fault modeling and simulation for crosstalk
in system-on-chip interconnects. Proceedings of IEEE/ACM International Conference on
Computer Aided Design, November 7–11, San Jose, CA, IEEE, pp. 297–303.
Dally, W. J. and Poulton, J. H. 1998. Digital Systems Engineering. Cambridge University
Press, Cambridge, UK.
Dally, W. J. and Towles, B. 2004. Principles and Practices of Interconnection Networks.
Morgan Kaufmann Publishers, San Francisco, CA.
Fick, D., Orio, A. D., Chen, G., Bertacco, V., Sylvester, D., and Blaauw, D. 2009.
A highly resilient routing algorithm for fault-tolerant NoCs. Proceedings of
Design, Automation and Test in Europe Conference, April 20–24, Nice, France, IEEE,
pp. 21–26.
Fukushima, Y., Fukushi, M., and Horiguchi, S. 2009. Fault-tolerant routing algorithm
for network on chip without virtual channels. Proceedings of IEEE International
Symposium on Defect and Fault Tolerance in VLSI Systems, October 7–9, Chicago,
IL, IEEE, pp. 313–321.
Ganguly, A., Pande, P. P., Belzer, B. and Grecu, C. 2007. Addressing signal integrity in
networks on chip interconnects through crosstalk-aware double error correction
coding. Proceedings of IEEE Computer Society Annual Symposium on VLSI, March
9–11, Porto Alegre, Brazil, IEEE, pp. 317–324.
Glass, C. J. and Ni, L. 1996. Fault-tolerant wormhole routing in meshes without virtual channels. IEEE Transaction on Parallel and Distributed Systems, vol. 7, no. 6,
pp. 620–635.
Hedge, R. and Shanbhag, N. R. 2000. Toward achieving energy efficiency in presence
of deep submicron noise. IEEE Transactions on Very Large Scale Integration (VLSI)
Systems, vol. 8, no. 4, pp. 379–391.
Huang, P. T., Fang, W. L., Wang, Y. L. and Hwang, W. 2008. Low power and reliable
interconnection with self-corrected green coding scheme for network-on-chip.
Proceedings of ACM/IEEE International Symposium on Networks-on-Chip, April
7–10, Newcastle upon Tyne, IEEE, pp. 77–83.
Ismail, Y. I., Friedman, E. G., and Neves, J. L. 1998. Figures of merit to characterize the
importance of on-chip inductance. Proceedings of Design Automation Conference,
June 15–19, San Francisco, CA, IEEE, pp. 560–565.
Joshi, S. M., Dubey, P. K., and Kaplan, M. A. 2000. A new parallel algorithm for
CRC generation. IEEE International Conference on Communication, June 18–22,
New Orleans, LA, IEEE, pp. 1764–1768.
Kumar, S. V., Kim, C. H., and Sapatnekar, S. S. 2006. An analytical model for negative
bias temperature instability. Proceedings of IEEE/ACM International Conference on
Computer Aided Design, pp. 493–496.
Lee, S. J., Lee, K., and Yoo, H. J. 2005. Analysis and implementation of practical,
cost-effective networks on chips. IEEE Design & Test Computers, vol. 22, no. 5,
pp. 422–433.
Lin, S. and Costello, D. J. 1983. Error Control Coding: Fundamentals and Applications.
Prentice Hall, New Jersey.