231
Signal Integrity and Reliability of Network-on-Chip
NoC platform. Among the signal integrity issues, it has presented a detailed
study of capacitive crosstalk effects on the NoC link and avoidance techniques. This chapter also focused on the effects of soft error and correction
techniques in latches, flip-flops, combinational logic, and SRAM. It has discussed about the error detection and correction approaches due to transient
faults. To address crosstalk avoidance, power minimization in the links, and
reliability in communication jointly, it highlights a unified coding framework. A number of joint coding schemes have been discussed to address the
signal integrity issues. As error correction techniques enhance the reliability of on-chip interconnects to some degree, these will allow the designers
to go for power consumption and reliability trade-off. The error correction
techniques allow decreasing the voltage swing of signal, and at the same
time guaranteeing the reliability of the encoded data under the same reliability level of uncoded data. The energy reliability trade-off of different
coding techniques has also been discussed. Thus, this chapter surveys the
full gamut of research carried out to address signal integrity and reliability
issues in NoC design of DSM technology.
Chapter 8 will focus on the challenges of NoC testing in achieving a sufficient fault coverage under a set of fault models relevant to NoC characteristics, under constraints such as test time, test power dissipation, less area over
head, and test resources.
References
Albertengo, G. and Sisto, R. 1990. Parallel CRC generation. IEEE Micro, vol. 10, no. 5,
pp. 63–71.
Ali, M., Welzl, M., and Hessler, S. 2007a. A fault tolerant mechanism for handling
permanent and transient failures in a network on chip. Proceedings of IEEE
International Conference on Information Technology, April 2–4, Las Vegas, NV,
IEEE, pp. 1027–1032.
Ali, M., Welzl, M., Hessler, S., and Hellebrand, S. 2007b. An efficient fault tolerant
mechanism to deal with permanent and transient failures in a network on chip.
International Journal of High Performance Systems Architecture, vol. 1, no. 2, pp.
113–123.
Asadi, H. and Tahoori, M. 2006. Soft error derating computation in sequential circuits. Proceedings of IEEE/ACM International Conference on Computer Aided Design,
November 5–9, San Jose, CA, IEEE, pp. 497–501.
Benini, L. and Micheli, G. D. 2006. Networks on Chips: Technology and Tools. Morgan
Kaufmann Publishers, San Francisco, CA.
Bertozzi, D. and Benini, L. 2004. Xpipes: A network-on-chip architecture for gigascale
system-on-chip. IEEE Circuits and Systems Magazine, vol. 4, no. 2, pp. 18–21.
Campobello, G., Patane, G., and Russo, M. 2003. Parallel CRC realization. IEEE
Transactions on Computers, vol. 52, no. 10, pp. 1312–1319.
Signal Integrity and Reliability of Network-on-Chip
NoC platform. Among the signal integrity issues, it has presented a detailed
study of capacitive crosstalk effects on the NoC link and avoidance techniques. This chapter also focused on the effects of soft error and correction
techniques in latches, flip-flops, combinational logic, and SRAM. It has discussed about the error detection and correction approaches due to transient
faults. To address crosstalk avoidance, power minimization in the links, and
reliability in communication jointly, it highlights a unified coding framework. A number of joint coding schemes have been discussed to address the
signal integrity issues. As error correction techniques enhance the reliability of on-chip interconnects to some degree, these will allow the designers
to go for power consumption and reliability trade-off. The error correction
techniques allow decreasing the voltage swing of signal, and at the same
time guaranteeing the reliability of the encoded data under the same reliability level of uncoded data. The energy reliability trade-off of different
coding techniques has also been discussed. Thus, this chapter surveys the
full gamut of research carried out to address signal integrity and reliability
issues in NoC design of DSM technology.
Chapter 8 will focus on the challenges of NoC testing in achieving a sufficient fault coverage under a set of fault models relevant to NoC characteristics, under constraints such as test time, test power dissipation, less area over
head, and test resources.
References
Albertengo, G. and Sisto, R. 1990. Parallel CRC generation. IEEE Micro, vol. 10, no. 5,
pp. 63–71.
Ali, M., Welzl, M., and Hessler, S. 2007a. A fault tolerant mechanism for handling
permanent and transient failures in a network on chip. Proceedings of IEEE
International Conference on Information Technology, April 2–4, Las Vegas, NV,
IEEE, pp. 1027–1032.
Ali, M., Welzl, M., Hessler, S., and Hellebrand, S. 2007b. An efficient fault tolerant
mechanism to deal with permanent and transient failures in a network on chip.
International Journal of High Performance Systems Architecture, vol. 1, no. 2, pp.
113–123.
Asadi, H. and Tahoori, M. 2006. Soft error derating computation in sequential circuits. Proceedings of IEEE/ACM International Conference on Computer Aided Design,
November 5–9, San Jose, CA, IEEE, pp. 497–501.
Benini, L. and Micheli, G. D. 2006. Networks on Chips: Technology and Tools. Morgan
Kaufmann Publishers, San Francisco, CA.
Bertozzi, D. and Benini, L. 2004. Xpipes: A network-on-chip architecture for gigascale
system-on-chip. IEEE Circuits and Systems Magazine, vol. 4, no. 2, pp. 18–21.
Campobello, G., Patane, G., and Russo, M. 2003. Parallel CRC realization. IEEE
Transactions on Computers, vol. 52, no. 10, pp. 1312–1319.