Signal Integrity and Reliability of Network-on-Chip
229
As error correction techniques enhance the reliability of on-chip interconnects
to some degree, these will allow the designers to go for power consumption and
reliability trade-off. For a given σ N
2 , the bit error probability increases by decreasing the voltage swing of signals. The error correction techniques allow decreasing
the voltage swing of signal and guaranteeing the reliability at the same time if and
only if Equation 7.3 satisfies where P uncoded (ε) is the probability of word errors in
the uncoded case with full swing voltage and P ecc ( ε ) is the residual word error
probability with ECC at lower swing voltage ( V DD ) :
ε
( )
(7.3)
P uncoded ( ) ≥ P ecc ε
In order to obtain the lowest supply voltage for a specific error correction
technique under the same level reliability of uncoded data, the supply voltage can be written as
Q
−1 ( )
ε
V DD = V DD ×
such that ecc ε
uncoded ( )
−1
P ( ) = P
ε
(7.4)
Q ( )
ε
In the above equation, V DD is the nominal supply voltage in the absence of any
coding technique such that P ecc (ε) = P uncoded (ε). Therefore, to compute the
V DD or a specific coding scheme, the residual word error probability needs
to be computed. For example, for a k-bit link, the residual word error probabilities for a small bit error rate (ε) of uncoded, hamming, DAP, CADEC, and
2 2
2
2
3
Self-corrected green coding schemes are kε, k ε , 3 ( + 1 ε / , k
k k ) 2
(k − 4)ε ,
and (3kε
2
− 2kε
3 ), respectively.
Ganguly et al. (2007) showed that as CADEC has higher error correction
capability compared to DAP, it allows maximum voltage swing reduction.
Although an individual bit error probability in the random bit error rate
model is independent of each other, in a burst error scenario this consideration is no longer valid and demands for a burst word error rate model. The
burst word error probability of the above error correction scheme has been
formulated below.
Assuming an individual bit error rate to be є, the probability that a burst
i
n−i
error has affected i consecutive lines in an n-bit link (i  ≤ n) is ∈ (1−∈ ) .
Thus, the total burst error probability of any of the i consecutive lines getting affected can be computed by varying the set of lines under consideration. Thus, for a specific value of i (i  < n), the word error probability is
i
n−i)
n× ∈ ×(1 −∈ )
(
, whereas, for i = n, there is only one combination. Figure 7.22
shows a burst error correction scheme with an interleaving degree of 8,
which can correct errors in at most eight adjacent wires whose link width n
is 56. If the burst length is more than 8, the above scheme will fail. Therefore,
the burst word error probability can be written as
⎡
55
⎤
i
56− i
56
P burst word error = 56 × ⎢ ∑ ∈ (1−∈ ) ⎥ +∈
(7.5)
⎢
⎥
⎣ i=9
⎦