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Signal Integrity and Reliability of Network-on-Chip
k
m
m
n
Invert
lines
p
q
FPC
LPC
(1)
inv
inv
LPC
(4)
(1)
FPC
(2)
FPC
(7)
FPC
(8)
CAC
(FPC)
CAC
(FPC)
LPC
(BI)
32 bits
4–5
4–5
4–5
4–5
62 bits
Figure 7.24
Joint CAC and LPC scheme.
mesh-based NoC at 130-nm technology. A thorough cost evaluation has been
carried out with varying λ, where λ is the ratio of coupling capacitance to
bulk capacitance. Any coding scheme is energy efficient if (E uncoded – E coded )/
E codec > 1, where E uncoded , E coded , and E codec denote the energy consumptions
of uncoded link, coded link, and codec module, respectively. They observed
that for FOC to be energy efficient at 130-nm technology, the value of λ has
to be greater than 4. At λ = 4, FOC is not energy efficient, whereas both FPC
and FTC are energy efficient. Energy savings in FTC scheme is the highest
and FPC occupies the second position among the three. However, FPC can
be combined with BI-based LPC schemes. This is because inverting an FPC
code word maintains the FP condition. In a joint code with FPC and BI-based
LPC, the invert bits are encoded using duplication code to avoid crosstalk
delay in the invert bits, as shown in Figure 7.24. The joint code is a concatenation of the two component codes and no further optimization is possible.
The codec overhead of the joint code is the sum of codec overheads of the
component codes, and hence, the joint code is complex.
7.5.2 Joint LPC and eCC Scheme (LPC + eCC)
The joint LPC and ECC scheme is shown in Figure  7.25a. Here, BI and
Hamming SEC codes are combined. The scheme is called BI Hamming
(BIH) code (Sridhara and Shanbhag 2005). These codes are suitable for long
DSM buses where reduction of power consumption is important but voltage scaling is not possible due to the presence of DSM noise. A property
of XOR operation is that if an odd (even) number of inputs of an XOR gate
are inverted, then the output is inverted (unchanged). Therefore, after computing the invert bit from the BI code, the output odd parity bit is conditionally inverted using the invert bit. Thus, parity generation and invert bit