210
Network-on-Chip
of both master and slave stages to correct soft errors in combinational logic,
as well as soft errors in master and slave latches.
7.4.2 inter-router Link error Control
As discussed earlier in Section 7.2.3.1, capacitive crosstalk is one of the major
sources of a transient fault in NoC links. It introduces crosstalk noise (glitch),
crosstalk delay (both speedup and slowdown) that can violate the setup and
hold requirements of any design, and double switching error. Several techniques have been proposed in literature to mitigate the ill effect of capacitive
crosstalk and will be covered in Section 7.4.2.1.
7.4.2.1 Capacitive Crosstalk Avoidance Techniques
The capacitive crosstalk avoidance techniques can be categorized as follows:
1. Usage of shielding and duplicating wire
2. Increase of inter-wire spacing
3. Increase (decrease) of the driver strength of the victim (aggressor)
nets
4. Usage of on-chip serialized link
5. Crosstalk avoidance code (CAC)
Each of the above techniques is described as follows:
1. Usage of shielding and duplicating wire is one of the most common
approaches to mitigate capacitive crosstalk. In the shielding technique, a ground or supply wire is inserted after every signal wire.
In the duplicating method, each signal wire is duplicated. Hence,
shielding and duplicating techniques will cause double the bus
width. Another shielding technique is half shielding, in which a
ground wire is inserted after every two signal wires. Shielding and
duplicating can be combined together to form a duplicate-and-shield
technique. Though simple, this method has the disadvantage of
requiring a significant number of extra wires. Applying the above
methods in a three-wire model, there is no opposite transitions (↑ ↓ ↑
or ↓ ↑ ↓) in all three wires, and hence can achieve different degrees of
delay reduction. The glitch width and height are also lesser than the
worst-case pattern. Table 7.2 depicts different shielding and duplicating methods described above for an 8-bit data word and also
shows the length of the code word (n) along with the delay in the
victim line, assuming that the impact of nonadjacent aggressors has
negligible impact on the victim wire.
Network-on-Chip
of both master and slave stages to correct soft errors in combinational logic,
as well as soft errors in master and slave latches.
7.4.2 inter-router Link error Control
As discussed earlier in Section 7.2.3.1, capacitive crosstalk is one of the major
sources of a transient fault in NoC links. It introduces crosstalk noise (glitch),
crosstalk delay (both speedup and slowdown) that can violate the setup and
hold requirements of any design, and double switching error. Several techniques have been proposed in literature to mitigate the ill effect of capacitive
crosstalk and will be covered in Section 7.4.2.1.
7.4.2.1 Capacitive Crosstalk Avoidance Techniques
The capacitive crosstalk avoidance techniques can be categorized as follows:
1. Usage of shielding and duplicating wire
2. Increase of inter-wire spacing
3. Increase (decrease) of the driver strength of the victim (aggressor)
nets
4. Usage of on-chip serialized link
5. Crosstalk avoidance code (CAC)
Each of the above techniques is described as follows:
1. Usage of shielding and duplicating wire is one of the most common
approaches to mitigate capacitive crosstalk. In the shielding technique, a ground or supply wire is inserted after every signal wire.
In the duplicating method, each signal wire is duplicated. Hence,
shielding and duplicating techniques will cause double the bus
width. Another shielding technique is half shielding, in which a
ground wire is inserted after every two signal wires. Shielding and
duplicating can be combined together to form a duplicate-and-shield
technique. Though simple, this method has the disadvantage of
requiring a significant number of extra wires. Applying the above
methods in a three-wire model, there is no opposite transitions (↑ ↓ ↑
or ↓ ↑ ↓) in all three wires, and hence can achieve different degrees of
delay reduction. The glitch width and height are also lesser than the
worst-case pattern. Table 7.2 depicts different shielding and duplicating methods described above for an 8-bit data word and also
shows the length of the code word (n) along with the delay in the
victim line, assuming that the impact of nonadjacent aggressors has
negligible impact on the victim wire.