Weak
Weak
keeper
keeper
Latch
Latch
IN1
Latch
Latch
Clock
1D
C1
C
C
C-element
C-element
Q
1D
C1
Q
1D
OUT
C1
Q
1D
C1
Q
τ
209
Signal Integrity and Reliability of Network-on-Chip
down to the correct value (because a path shorter than the timing critical
path has been exercised here) and the C-element output is charged to a correct value, a hazard appears at OUT3 (and at OUT4 after time τ) due to a soft
error inside the combinational logic. Suppose that the hazard settles down to
the correct value within τ time units. In this case, correct logic value will be
preserved on C-OUT since the hazards at OUT3 and OUT4 will not overlap.
Figure 7.13 describes this scenario.
Figure 7.14 shows a flip-flop design for implementing soft error correction
using time-shifted outputs. C-elements and keepers are added at the outputs
Hazard
due to
soft error
Hazard blocked
by C-element
OUT settles to
correct value
OUT3
C-OUT
< τ
<τ
τ
τ
OUT4
Clock edge
Figure 7.13
Soft error correction using time-shifted output.
Figure 7.14
Soft error correction in combinational logic and flip-flop using time-shifted output.