V cc
C-OUT
GND
(a)
A
B
A B
C-OUT
0
0
0
0
1
Previous value retained
1
0
Previous value retained
1
1
1
(b)
207
Signal Integrity and Reliability of Network-on-Chip
Figure 7.9
Structure of C-element (a) and the truth table (b).
Combination
logic
Clock
OUT
Latch
1D
C1
Q
1D
C1
Q
B
A
Weak keeper
C
C-OUT
C-element
Redundant latch
(scan reuse)
IN
Figure 7.10
Soft error correction in latches.
are same, the output (C-OUT) will follow the inputs; otherwise, the output
will latch at its previous value. Mitra et al. (2006a) presented the soft error
correction in latches using C-element and a redundant latch as shown in
Figure 7.10. If soft error affects any of the latches at a time, the output of the
latches will differ and the C-OUT will retain to its previous value, and hence
error will not propagate to the next stage. The correct logic value will be held
at C-OUT by the keeper. Soft error in the keeper does not have a major effect
because the C-element output will be strongly driven by the latch contents.
The cost associated with the redundant latch is minimized by reusing onchip resources such as scan for multiple functions at various stages of manufacturing and field use (Mitra et al. 2005).
As discussed in Section 7.2.3.2, soft error in combinational logic will cause a
SET pulse. The transient pulse, after propagation through the logic, can be captured by a latch or a flip-flop. Hence, it is desirable to address soft error protection in flip-flops, latches, and combinational logic jointly. Otherwise, separate
protection techniques for flip-flops, latches, and combinational logic introduce
additional penalties and design complexity. Soft errors in combinational logic
can be corrected using two techniques: (1) error correction using duplication and
C-OUT
GND
(a)
A
B
A B
C-OUT
0
0
0
0
1
Previous value retained
1
0
Previous value retained
1
1
1
(b)
207
Signal Integrity and Reliability of Network-on-Chip
Figure 7.9
Structure of C-element (a) and the truth table (b).
Combination
logic
Clock
OUT
Latch
1D
C1
Q
1D
C1
Q
B
A
Weak keeper
C
C-OUT
C-element
Redundant latch
(scan reuse)
IN
Figure 7.10
Soft error correction in latches.
are same, the output (C-OUT) will follow the inputs; otherwise, the output
will latch at its previous value. Mitra et al. (2006a) presented the soft error
correction in latches using C-element and a redundant latch as shown in
Figure 7.10. If soft error affects any of the latches at a time, the output of the
latches will differ and the C-OUT will retain to its previous value, and hence
error will not propagate to the next stage. The correct logic value will be held
at C-OUT by the keeper. Soft error in the keeper does not have a major effect
because the C-element output will be strongly driven by the latch contents.
The cost associated with the redundant latch is minimized by reusing onchip resources such as scan for multiple functions at various stages of manufacturing and field use (Mitra et al. 2005).
As discussed in Section 7.2.3.2, soft error in combinational logic will cause a
SET pulse. The transient pulse, after propagation through the logic, can be captured by a latch or a flip-flop. Hence, it is desirable to address soft error protection in flip-flops, latches, and combinational logic jointly. Otherwise, separate
protection techniques for flip-flops, latches, and combinational logic introduce
additional penalties and design complexity. Soft errors in combinational logic
can be corrected using two techniques: (1) error correction using duplication and