206
Network-on-Chip
in NoC, FIFOs are two-port memory—one write-only port and one
read-only port. A transient fault can affect different parts of a FIFO,
for example, the memory cells, the addressing mechanism, full and
empty signal generation logic, and read/write enable signals. A single soft error within the FIFO will produce a SEU. A double (or more)
error, however, would require more protection technique.
5. VCA error: The VCA, like the routing unit, operates only on header
flits. All new packets request access to any one of the valid output
VCs. The VCA arbitrates between all those packets requesting the
same output VC. The VCA maintains the states of all successful allocations through a pairing between input VCs and allocated output
VCs. Soft errors within the VCA may give rise to following scenarios:
a. A soft error may assign one input VC to an invalid output VC.
Such an assignment will block further traversal of the packet
through the network.
b. An unreserved output VC may be assigned to two different
input VCs due to soft error. This will lead to packet mixing, and
eventually packet/flit loss.
c. Transient error may cause a reserved output VC to be assigned to
a requesting input VC. This case is very similar to case (b) above.
6. Error in control logic and handshaking signals: Every router has several
control logic inside it. These control logic blocks consist of combinational and sequential elements. The routers communicate with other
neighboring routers by the handshaking signal lines to facilitate proper
functionality and synchronization. Transient faults in the control logic
and handshaking lines would disrupt the operation of the network.
As most of the transient faults inside the NoC router are caused by soft error,
Section 7.4.1.1 describes the soft error correction techniques in latch, flip-flop,
SRAM, and combinational logic.
7.4.1.1 Soft Error Correction
This section focuses on logic soft error protection—soft errors in latches, flipflops, and combinational logic. Soft errors in SRAMs are protected using
parity or error-correcting codes with interleaving. For a latch, as discussed
in Section 7.2.3.2, the Q output is strongly driven by the D input during the
active cycle of the clock and the latch is not susceptible to soft errors. In the
inactive cycle when the output is latched to its previous state, soft error can
cause a SEU. Mitra et al. (2006a) proposed a built-in soft error resilience (BISER)
technique to protect the latches in the design using C-element. C-element is
a special type of hardware where two PMOS and two NMOS transistors are
connected in series. A two-input C-element and its truth table are shown in
Figure 7.9. From the truth table, it is clear that if both the inputs of C-element
Network-on-Chip
in NoC, FIFOs are two-port memory—one write-only port and one
read-only port. A transient fault can affect different parts of a FIFO,
for example, the memory cells, the addressing mechanism, full and
empty signal generation logic, and read/write enable signals. A single soft error within the FIFO will produce a SEU. A double (or more)
error, however, would require more protection technique.
5. VCA error: The VCA, like the routing unit, operates only on header
flits. All new packets request access to any one of the valid output
VCs. The VCA arbitrates between all those packets requesting the
same output VC. The VCA maintains the states of all successful allocations through a pairing between input VCs and allocated output
VCs. Soft errors within the VCA may give rise to following scenarios:
a. A soft error may assign one input VC to an invalid output VC.
Such an assignment will block further traversal of the packet
through the network.
b. An unreserved output VC may be assigned to two different
input VCs due to soft error. This will lead to packet mixing, and
eventually packet/flit loss.
c. Transient error may cause a reserved output VC to be assigned to
a requesting input VC. This case is very similar to case (b) above.
6. Error in control logic and handshaking signals: Every router has several
control logic inside it. These control logic blocks consist of combinational and sequential elements. The routers communicate with other
neighboring routers by the handshaking signal lines to facilitate proper
functionality and synchronization. Transient faults in the control logic
and handshaking lines would disrupt the operation of the network.
As most of the transient faults inside the NoC router are caused by soft error,
Section 7.4.1.1 describes the soft error correction techniques in latch, flip-flop,
SRAM, and combinational logic.
7.4.1.1 Soft Error Correction
This section focuses on logic soft error protection—soft errors in latches, flipflops, and combinational logic. Soft errors in SRAMs are protected using
parity or error-correcting codes with interleaving. For a latch, as discussed
in Section 7.2.3.2, the Q output is strongly driven by the D input during the
active cycle of the clock and the latch is not susceptible to soft errors. In the
inactive cycle when the output is latched to its previous state, soft error can
cause a SEU. Mitra et al. (2006a) proposed a built-in soft error resilience (BISER)
technique to protect the latches in the design using C-element. C-element is
a special type of hardware where two PMOS and two NMOS transistors are
connected in series. A two-input C-element and its truth table are shown in
Figure 7.9. From the truth table, it is clear that if both the inputs of C-element