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Signal Integrity and Reliability of Network-on-Chip
7.4 Transient Fault Controlling Techniques
Primarily two types of transient faults can upset the on-chip network infrastructure: (1) intra-router errors occur within individual router components
and (2) inter-router link errors occur during flit traversal.
7.4.1 intra-router error Control
In NoC, VC-based routers are widely used. The details of a VC-based router
architecture have been described in Chapter 3. It consists of a routing control
unit, a switch arbiter (SA), a crossbar, an input buffer (FIFO), a VC allocator
(VCA), a control logic, and handshaking signals. Park et al. (2006) focused on
the possible errors in different modules of a NoC router and their controlling
strategies as summarized below.
1. Routing control unit error: The routing control unit looks into the
packet header to select the next router. The routing operation may be
table based or algorithm based. A transient fault in the routing unit
logic may cause a packet to be misdirected.
2. SA error: Depending on the packet header, the routing unit sends a
request to the SA block. There may be a possibility that more than
one requester can send their requests to access the same output
channel. Thus, the SA block performs arbitration to select one of
them and sends a grant signal to it. A transient fault in SA may give
rise to the following conditions:
a. A soft error in the control signals of the switch allocator can
prevent flits from traversing the crossbar. This case is the least
problematic, since the flits will keep on requesting access to the
crossbar until they succeed.
b. If a payload flit is mistakenly sent to a direction different from
the header flit, it would cause flit/packet loss as it would deviate
from the wormhole created by its header flit.
c. An error can cause the arbiter to send a flit to multiple outputs
(multicasting). If the flit is a payload flit, the same error will occur
as in case (b). If the flit is a header flit, multiple VCs will mistakenly be reserved in all the receiving routers. The VCs will stay
permanently reserved, thus reducing the effective buffer space
in those routers.
3. Crossbar error: A transient fault in the crossbar may produce glitch in
data transmission.
4. FIFO error: FIFO can be implemented as register banks or dedicated
SRAM arrays. Due to the unidirectional nature of communication
Signal Integrity and Reliability of Network-on-Chip
7.4 Transient Fault Controlling Techniques
Primarily two types of transient faults can upset the on-chip network infrastructure: (1) intra-router errors occur within individual router components
and (2) inter-router link errors occur during flit traversal.
7.4.1 intra-router error Control
In NoC, VC-based routers are widely used. The details of a VC-based router
architecture have been described in Chapter 3. It consists of a routing control
unit, a switch arbiter (SA), a crossbar, an input buffer (FIFO), a VC allocator
(VCA), a control logic, and handshaking signals. Park et al. (2006) focused on
the possible errors in different modules of a NoC router and their controlling
strategies as summarized below.
1. Routing control unit error: The routing control unit looks into the
packet header to select the next router. The routing operation may be
table based or algorithm based. A transient fault in the routing unit
logic may cause a packet to be misdirected.
2. SA error: Depending on the packet header, the routing unit sends a
request to the SA block. There may be a possibility that more than
one requester can send their requests to access the same output
channel. Thus, the SA block performs arbitration to select one of
them and sends a grant signal to it. A transient fault in SA may give
rise to the following conditions:
a. A soft error in the control signals of the switch allocator can
prevent flits from traversing the crossbar. This case is the least
problematic, since the flits will keep on requesting access to the
crossbar until they succeed.
b. If a payload flit is mistakenly sent to a direction different from
the header flit, it would cause flit/packet loss as it would deviate
from the wormhole created by its header flit.
c. An error can cause the arbiter to send a flit to multiple outputs
(multicasting). If the flit is a payload flit, the same error will occur
as in case (b). If the flit is a header flit, multiple VCs will mistakenly be reserved in all the receiving routers. The VCs will stay
permanently reserved, thus reducing the effective buffer space
in those routers.
3. Crossbar error: A transient fault in the crossbar may produce glitch in
data transmission.
4. FIFO error: FIFO can be implemented as register banks or dedicated
SRAM arrays. Due to the unidirectional nature of communication