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the output of the gate (nominal FIT); this glitch has to propagate through the
combinational logic to the flip-flop inputs (LD); and finally this erroneous
glitch must be captured in a flip-flop, that is, the erroneous transient must
have a sufficient overlap with the latching window of the flip-flop (TD). The
SER of each element is given by the following relation:
Individual elements FIT = Nominal FIT
’
× TD × LD
In general, TD and LD are not independent, and hence accurate analysis
requires the concept of TD–LD (Asadi and Tahoori 2006). A combinational
logic (static CMOS based), by itself, cannot cause a SEU. The gate can suffer a
glitch that might propagate downstream and be captured by a flop as shown
in Example 7.2.
Example 7.2
Figure 7.8 shows the output of gate A (OR gate) is affected to soft error.
The width of the soft error-induced glitch at this node is W. The propagation probability of the glitch at the output of gate D (AND gate) is
the product of the probability at the output of gate B being 1 (SP B = 0.2;
the probability of the output of gate B being 1) and the propagation
probability of the glitch (here, 1 × 0.2 = 0.2). Similarly, the propagation probability at the output of the gate E (OR gate) is calculated as
0.2 × (1 – SP C ) = 0.2 × 0.6 = 0.12 (the probability of the output of gate
C being 1). Hence, the LD factor is 0.12. The underlying assumption
in this example is the value of all signals other than on-path signals
(which propagated the erroneous glitch) is stable.
* * *
The TD is the probability that an erroneous value is captured in the
flop. It can be calculated based on the setup (S) and hold (H) times of the
flop, the glitch width (W 1 ), and the clock period (T). Glitch width at flop
input (W 1 ) can be different from that at its origin (node A in Figure 7.8)
due to various rise and fall transition delays for the gates along the path.
The TD factor is defined as TD = (S + H + W 1 )/T. The error propagation
B
A
W
W 1
C
E
FF
D
SP B = 0.2
SP C = 0.4
Figure 7.8
Propagation of glitch through logic gates to flip-flop (FF).