203
Signal Integrity and Reliability of Network-on-Chip
probability is calculated as the product of the LD and the TD. If there are
multiple paths from the error site to the flip-flop, the overall error propagation probability is the product of individual paths’ error propagation
probability.
7.2.3.3 Some Other Sources of Transient Faults
7.2.3.3.1 PVT Variation
Process, supply voltage, and temperature variations are other important
sources of timing fault for any VLSI circuit. The delay of a transistor in a slow
process will be more than that in a fast process. With increasing temperature,
both the transistor and interconnect delays will increase in 65-nm and above
technologies. Of course, in 40-nm and lower geometries, temperature inversion can be observed. The delay of the transistor in 40-nm geometry will be
more in cold condition than that in hot condition. But interconnect delay will
keep on increasing with increasing temperature in those technologies. Thus,
it is mandatory to do proper timing analysis for meeting the timing requirements in all possible sign-off corners.
7.2.3.3.2 Synchronization Failure
Any multicore design has several clock domains and the cores communicate
with each other through globally asynchronous and locally synchronous
(GALS) style. The communication can suffer due to synchronization errors,
and hence synchronizers are required between the clock domains. Several
types of synchronizers including dual-clock FIFO synchronizers, delay-line
synchronizers, and simple pipeline synchronizers have been proposed by
Dally and Poulton (1998). To avoid synchronization failure, synchronizers
should be properly designed and well tested.
7.2.3.3.3 Power Supply Noise
Power supply noise is an important source of a transient error in any VLSI circuit. Noise in ground and power lines is known as ground bounce and power
bounce, respectively. With fluctuating supply and ground voltages, the delay
of the data path is affected, which may cause timing violation. Decoupling
capacitance (on-chip or on-package) reduces power supply voltage noise.
7.2.3.3.4 IR Drop
Another major cause of signal integrity is the IR drop effect caused by wire
resistance and current drawn from the power and ground grids. If the wire
resistance is too large or the cell current is higher than predicted, an undesirable voltage drop may happen. The voltage drop causes the voltage supplied
to the affected cells to be lower than required, which leads to larger gate
and signal delays, which in turn can cause timing fault in the signal paths
as well as clock skew. Voltage drop on power and ground grids can also
Signal Integrity and Reliability of Network-on-Chip
probability is calculated as the product of the LD and the TD. If there are
multiple paths from the error site to the flip-flop, the overall error propagation probability is the product of individual paths’ error propagation
probability.
7.2.3.3 Some Other Sources of Transient Faults
7.2.3.3.1 PVT Variation
Process, supply voltage, and temperature variations are other important
sources of timing fault for any VLSI circuit. The delay of a transistor in a slow
process will be more than that in a fast process. With increasing temperature,
both the transistor and interconnect delays will increase in 65-nm and above
technologies. Of course, in 40-nm and lower geometries, temperature inversion can be observed. The delay of the transistor in 40-nm geometry will be
more in cold condition than that in hot condition. But interconnect delay will
keep on increasing with increasing temperature in those technologies. Thus,
it is mandatory to do proper timing analysis for meeting the timing requirements in all possible sign-off corners.
7.2.3.3.2 Synchronization Failure
Any multicore design has several clock domains and the cores communicate
with each other through globally asynchronous and locally synchronous
(GALS) style. The communication can suffer due to synchronization errors,
and hence synchronizers are required between the clock domains. Several
types of synchronizers including dual-clock FIFO synchronizers, delay-line
synchronizers, and simple pipeline synchronizers have been proposed by
Dally and Poulton (1998). To avoid synchronization failure, synchronizers
should be properly designed and well tested.
7.2.3.3.3 Power Supply Noise
Power supply noise is an important source of a transient error in any VLSI circuit. Noise in ground and power lines is known as ground bounce and power
bounce, respectively. With fluctuating supply and ground voltages, the delay
of the data path is affected, which may cause timing violation. Decoupling
capacitance (on-chip or on-package) reduces power supply voltage noise.
7.2.3.3.4 IR Drop
Another major cause of signal integrity is the IR drop effect caused by wire
resistance and current drawn from the power and ground grids. If the wire
resistance is too large or the cell current is higher than predicted, an undesirable voltage drop may happen. The voltage drop causes the voltage supplied
to the affected cells to be lower than required, which leads to larger gate
and signal delays, which in turn can cause timing fault in the signal paths
as well as clock skew. Voltage drop on power and ground grids can also