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Signal Integrity and Reliability of Network-on-Chip
0
1
0
0
0
0
0
0
0
1
Q
Q
clk
clk
1
D
1
D
Q
Q
Figure 7.7
Soft error in D-type latch.
latched, soft error can invert the logic stored in the latch and causes a SEU as
shown in Figure 7.7.
In combinational logic, a particle strike suffices to flip the logic value of a
node, creating a single-event transient (SET) pulse. The transient pulse, after
propagation through the logic, can be captured by a latch or flip-flop. With
each technology generation, the transient pulses become wider with respect
to logic transition time of the logic gates. In addition, as the clock frequency
increases, the probability of latching a transient pulse increases as well. Due
to these trends, the error rates in logic parts become as high as the error
rates in memories. The details of logic soft error correction in NoC router are
described in Section 7.4.1.1.
Depending on the soft error protection technique in a system, an effect
of soft error can be classified into three types: (1) detected/corrected,
(2) detected/uncorrected, and (3) undetected. The detected/corrected
errors are typically associated with error correction logic. The detected/
uncorrected errors often originate from parity protection since parity in
most cases can detect but cannot correct the error. This type of error can
result in a system reset or an application termination, depending on the
severity of the error. The undetected errors can result in nonrecoverable
errors causing system hangs or in silent data corruption (SDC) causing data
integrity problems. Error detection and correction techniques can be used
to cope with most of the logic soft errors, but at the same time, in a large
system it is difficult to directly apply these techniques because of associated performance degradation and cost (power and area) overhead.
Therefore, from a system point of view, it is very important to find out the
regions that are highly susceptible to soft errors and apply the protection
circuitry to meet the targeted MTBF (or FIT) at optimized performance
and cost degradation.
Estimation of soft error rate (SER) in sequential circuit is very challenging
since computation of the probability of erroneous system requires dynamic
analysis of transients. SER estimation of each element in a system mainly
depends on three factors: (1) nominal FIT, (2) logic derating (LD), and (3) timing
derating (TD) (Nguyen and Yagil 2003). Full-chip FIT rate is the summation
of individual elements’ FIT rate on die. Particle strike must cause a glitch at