200
Network-on-Chip
V DD
V DD
B
A
1
1
0
0
A
B
Figure 7.6
Soft error in a back-to-back inverter.
and neutrons generate electron–hole pairs along their path of traversal
while hitting the transistor’s diffusion. Neutrons are particularly troublesome as they tend to generate more charge than alpha particles and can
penetrate most man-made construction (a neutron can easily pass through
five feet of concrete). This effect varies with both latitude and altitude. In
London, the effect is 2 times worse than that on the equator. In Denver,
with its high altitude, the effect is 3 times worse than that at sea-level
San Francisco.
Traditionally, soft errors are considered as a major problem for dynamic
RAM (DRAM). As the technology goes toward ultra-DSM level and the
supply voltage also goes down, a significantly lower charge deposed by a
particle strike suffices to flip the logic value of a node, thus creating a transient pulse. The same phenomenon starts to affect the static RAMs (SRAMs).
Unlike capacitor-based DRAMs, SRAMs are cross-coupled devices that have
far less capacitance in each cell. The lower the capacitance, the greater the
likelihood that an alpha particle or neutron will cause a single-event upset
(SEU). Figure 7.6 shows how a soft error affects a back-to-back inverter-based
memory. Initially, node A is at logic 1 and node B is at logic 0. Due to injection
of the soft error, the logic value of node A flips which drives node B to invert
the logic. This inverted bit will remain in the memory even after a soft error
disappears.
Soft errors in latches and flip-flops are the major contributors of logic soft
errors. Figure  7.7 focuses on the soft error in D-type latch. The same discussion can also be extended to flip-flops. During positive cycle of a clock
(clk = 1), the Q output of a D-type latch is strongly driven by the D input. Soft
error during this period (clk = 1) can be treated as a glitch at the Q output but
does not cause any SEU. In the negative cycle (clk = 0) when the Q output is