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Network-on-Chip
7.2.1 Permanent Faults
Permanent faults, as the name suggests, originate from permanent damages
in the circuit. These damages result in physical changes in the circuit whose
behavior does not change with time. Broken wires, time-dependent dielectric
breakdowns, and electromagnetic interference (EMI) are the examples of permanent failures on chip. Long on-chip interconnects, typical in customized,
domain-specific irregular NoC topologies, are increasingly susceptible to EMI.
Short switch-to-switch links in regular networks are more immune to such noise
sources. Another cause of permanent fault is electromigration. Aluminum interconnects are highly affected from the electromigration effect, whereas modern
copper interconnect-based ICs rarely fail due to electromigration effects. The
permanent fault handling in NoC is described more detail in Section 7.3.
7.2.2 Faults due to Aging effects
Device reliability issues such as negative-bias temperature instability (NBTI)
and hot carrier injection (HCI) make circuit performance degrade as it ages
and have more severe effects with shrinking device sizes and voltage margins. In Sections 7.2.2.1 and 7.2.2.2, each of them is described briefly.
7.2.2.1 Negative-Bias Temperature Instability
The instability of p-type metal oxide semiconductor (PMOS) transistor parameters (e.g., threshold voltage, transconductance, saturation current, etc.) under
negative (inversion) bias and relatively high temperature has been well known
since the 1970s and has become a significant reliability concern in present-day
digital design.
When a PMOS transistor is biased in inversion (V gs = –V dd ), the dissociation
of Si—H bonds along the silicon–oxide interface causes the generation of interface traps. The rate of generation of these traps is accelerated by the temperature and the time of applied stress (PMOS is turn ON). These traps cause an
increase in the threshold voltage (V th ) of the PMOS transistors. An increase in
V th causes the circuit delay to degrade, and when this degradation exceeds a
certain limit, the circuit may fail to meet its timing specifications. This effect,
known as negative-bias temperature instability, has become a reliability issue
in high-performance digital IC design, especially in sub-130-nm technologies.
Since a digital circuit consists of millions of nodes with various signal probabilities and activity factors, the degradation of timing paths is not uniform. Logic
blocks in a circuit are currently designed by assuming a certain safety margin
in the timing specifications to account for NBTI-induced performance degradation. Kumar et al. (2006) proposed an analytical model for measuring the impact
of NBTI. Their simulation results on International Symposium on Circuits and
Systems benchmarks under a 70-nm technology show that NBTI causes a delay
degradation of about 8% in combinational logic-based circuits after 10 years.