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Signal Integrity and Reliability of Network-on-Chip
7.2.2.2 Hot Carrier Injection
HCI describes the phenomena by which carriers gain sufficient energy due
to increase in electric field and causes increase in velocity, which can leave
the silicon and are injected into the gate oxide. This occurs as carriers move
along the channel of metal oxide semiconductor field effect transistor and
experience impact ionization near the drain end of the device. Electrons are
trapped in the oxide and hence change the threshold voltage (increases for
n-type metal oxide semiconductor [NMOS] and decreases for PMOS). The
hot electron phenomenon can lead to a reliability problem, where the circuit
might fail to meet the timing requirement after being in use for some time.
7.2.3 Transient Faults
As the technology is approaching toward DSM with shrinking feature sizes,
scaling of supply voltages, increasing wire density, and faster clock rates, NoC
suffers from following transient faults: (1) slowdown or speedup in delay due
to crosstalk, (2) crosstalk noise, (3) single- or multi-event upset due to soft error,
(4) delay due to process–voltage–temperature (PVT) variation, (5) synchronization failure, (6) delay due to power supply noise, (7) IR drop, and so on.
7.2.3.1 Capacitive Crosstalk
In modern DSM technologies with shrinking feature sizes and decreasing
spacing between adjacent interconnects, the value of coupling capacitance
becomes dominant, which causes capacitive crosstalk. There are two major
deteriorating effects due to capacitive crosstalk—crosstalk noise and crosstalk delay. Cuviello et al. (1999) proposed a novel fault model, called maximum aggressor fault (MAF) model, which considers the effect of crosstalk
between a set of aggressor lines and a victim line. For a link consisting of
N wires, MAF model assumes the worst-case situation with one victim line
and (N – 1) aggressor lines where all the aggressor lines are switching in a
same direction. According to the MAF model, Figure 7.2 shows the possible
errors on the victim wire in a three-wire model.
A crosstalk effect causing a positive (negative) glitch in the victim line (Y 2 ),
which should ideally have a logic 0 (logic 1), due to a rising (falling) transition at the aggressor lines Y 1 and Y 3 as shown in Figure 7.2a. This glitch will
consider as crosstalk noise when the peak value of the glitch is high enough
to cross the switching threshold of the receiver. Moreover, the width of the
glitch is also an important factor. Wider glitch may drive the load capacitance
to a potential that can be interpreted as a different logic value. An analytical model of crosstalk positive glitch is shown in Figure 7.3. When a falling
transition is applied to input A in , the PMOS of the inverter driven by A in can
be modeled by its channel resistance, R p , connecting A to V DD ; the corresponding NMOS device is off. The inverter driven by V in can be modeled by