192
Network-on-Chip
from the side walls. The dielectric material used in most ICs is SiO 2 . Self- and
mutual inductances become prominent for some global signal wires routed
in top metal layers due to its lower resistance and faster signal transition
time with increasing frequencies. Ismail et al. (1998) proposed a two-sided
inequality (Equation 7.1) that determines the range of length of interconnect
(L) in which inductance effects are significant and the line can be modeled as
a transmission line.
t
2 L
r
< L <
s
(7.1)
2 L s ⋅C s
R C s
In the above relation, the range of interconnect length (L) depends on the parasitic resistance (R), self-inductance (L s ), and self-capacitance (C s ) of the wire per
unit length as well as the transition time (t r ) of the signal at the output of its
driver. Ismail et  al. (1998) also proposed that if the above inequality is nonexistent and Equation 7.2 holds true, the effect of inductance is not important for
any length of interconnect and the wire can be modeled as a distributed RC line.
t r >
4

⎛
⎜
⎝

L s
R

⎞
⎟
⎠

(7.2)

Example 7.1
Consider the following parasitic values for a wire segment: Resistance
(R) = 0.4926 MΩ/m, self-inductance (L s ) = 0.3743 μH/m, self-capacitance
(C s ) = 70.7918 pF/m, transition time (t r ) = 100 ps, and length (L) = 1 mm.
Determine the interconnect model whether it is a transmission line or a
distributed RC.
* * *
By putting the values of parasitic components, length, and transition
time, Equation 7.1 is nonexistent. Hence the wire cannot model as a
transmission line. Putting the values of R and L s , it shows that the wire
can be modeled as a distributed RC if t r > 3.04 ps which is true in this
case. Hence, the wire can be modeled as a distributed RC.
The details of on-chip interconnect in the DSM era are covered in literature.
The scope of this chapter is narrowed to on-chip interconnect in networkon-chip (NoC) design and related issues. It has been reported in the work
of Benini and Micheli (2006) that the impact of inductance in most on-chip
interconnects is negligible and can be modeled as a distributed RC wire as
shown in Figure 7.1.
The rest of this chapter is organized as follows: Section 7.2 describes the
sources of different types of faults such as permanent faults, faults due to
aging effect, and transient faults in DSM technology. Section 7.3 discusses
the techniques to handle the permanent faults. Section 7.4 describes the