7
Signal Integrity and Reliability
of Network-on-Chip
7.1 Introduction
In deep submicron (DSM) technology, the importance of on-chip wiring
(interconnect) becomes significant as it impacts the system performance and
cost to a big extent. With the technology shrinking, on-chip interconnect suffers from increased resistance due to decrease in metal cross-sectional area
and also suffers from increased capacitance if the metal height is not reduced
proportionally with metal spacing. Therefore, resistance-capacitance (RC)
parameter in interconnects plays an increasing role in system-on-chip (SoC)
performance as feature size scales. In integrated circuit (IC) packaging, usage
of multiple interconnection layers is a common trend in order to provide better connectivity. The metal layers are normally divided into three categories:
local, semi-global, and global interconnects. In SoC design, several cores [intellectual property (IP), memory, processor, etc.] are integrated on a single silicon die. Local wires are used for connecting intra-core modules. These wires
have minimum dimensions and pitch, hence highly resistive. Semi-global
wires are used for inter-core communication. These wires are usually longer than local interconnects and have lesser resistance. Global interconnects,
however, are used as supply and clock lines. The signals passing through
these wires traverse long distance. These wires have higher cross-sectional
area and hence lesser resistance. For a typical eight-layerd 90-nm UMC process, layers 1–3 are used for local interconnect, layers 4 and 5 for semi-global
interconnect, and the top layers are reserved for global interconnect.
Copper is the mostly used material for on-chip interconnects in very-largescale integration (VLSI) design. It has lesser resistivity compared to aluminum. An on-chip interconnect can be modeled as a distributed RC network
or a transmission line with the parasitic resistance, capacitance, and inductance. The resistance of a wire is proportional to its length L and inversely
proportional to its cross section A with width (W) and thickness (T). Selfcapacitance of a wire is defined as the summation of line-to-substrate capacitance, inter- and intra-layer coupling capacitance, and fringing capacitance
191
Signal Integrity and Reliability
of Network-on-Chip
7.1 Introduction
In deep submicron (DSM) technology, the importance of on-chip wiring
(interconnect) becomes significant as it impacts the system performance and
cost to a big extent. With the technology shrinking, on-chip interconnect suffers from increased resistance due to decrease in metal cross-sectional area
and also suffers from increased capacitance if the metal height is not reduced
proportionally with metal spacing. Therefore, resistance-capacitance (RC)
parameter in interconnects plays an increasing role in system-on-chip (SoC)
performance as feature size scales. In integrated circuit (IC) packaging, usage
of multiple interconnection layers is a common trend in order to provide better connectivity. The metal layers are normally divided into three categories:
local, semi-global, and global interconnects. In SoC design, several cores [intellectual property (IP), memory, processor, etc.] are integrated on a single silicon die. Local wires are used for connecting intra-core modules. These wires
have minimum dimensions and pitch, hence highly resistive. Semi-global
wires are used for inter-core communication. These wires are usually longer than local interconnects and have lesser resistance. Global interconnects,
however, are used as supply and clock lines. The signals passing through
these wires traverse long distance. These wires have higher cross-sectional
area and hence lesser resistance. For a typical eight-layerd 90-nm UMC process, layers 1–3 are used for local interconnect, layers 4 and 5 for semi-global
interconnect, and the top layers are reserved for global interconnect.
Copper is the mostly used material for on-chip interconnects in very-largescale integration (VLSI) design. It has lesser resistivity compared to aluminum. An on-chip interconnect can be modeled as a distributed RC network
or a transmission line with the parasitic resistance, capacitance, and inductance. The resistance of a wire is proportional to its length L and inversely
proportional to its cross section A with width (W) and thickness (T). Selfcapacitance of a wire is defined as the summation of line-to-substrate capacitance, inter- and intra-layer coupling capacitance, and fringing capacitance
191