190
Network-on-Chip
Sotiriadis, P. P. 2002. Interconnect modeling and optimization in deep submicron
technologies. Ph.D. Dissertation, Massachusetts Institute of Technology, Cambridge.
Sotiriadis, P. P. and Chandrakasan, A. 2000. Low power bus coding techniques considering inter-wire capacitances. Proceedings of the IEEE Custom Integrated Circuits
Conference, May 21-24, Orlando, FL, IEEE, pp. 507–510.
Sotiriadis, P. P. and Chandrakasan, A. 2002. A bus energy model for deep submicron
technology. IEEE Transaction on Very Large Scale Integration Systems, vol. 10, no. 3,
pp. 341–350.
Sridhara, S. R. and Shanbhag, N. R. 2005. Coding for system-on-chip networks: A unified framework. IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
vol. 13, no. 6, pp. 655–667.
Stan, M. R. and Burleson, W. P. 1995. Bus-invert coding for low-power I/O. IEEE
Transactions on Very Large Scale Integration (VLSI) System, vol. 3, no. 1, pp. 49–58.
Stratakos, A. 1998. High-efficiency low-voltage DC-DC conversion for portable applications. Ph D Thesis, University of California, Berkeley, CA.
Yoo, S. and Choi, K. 1999. Interleaving partial bus-invert Coding for low power reconfiguration of FPGAs. Proceedings of International Conference on VLSI and CAD,
October 26-27, Seoul, Republic of Korea, IEEE, pp. 549–552.
Yuan, C. P. and Cheng, Y. C. 2005. A voltage level converter circuit design with low
power consumption. Proceedings of International Conference on ASIC, October
24-27, Shanghai, People’s Republic of China, IEEE, pp. 358–359.
Zhang, Y., Lach, J., Skadron, K., and Stan, M. R. 2002. Odd/even bus invert with twophase transfer for buses with coupling. Proceedings of International Symposium on
Low Power Electronics and Design, Monterey, CA, IEEE, pp. 80–83.
Network-on-Chip
Sotiriadis, P. P. 2002. Interconnect modeling and optimization in deep submicron
technologies. Ph.D. Dissertation, Massachusetts Institute of Technology, Cambridge.
Sotiriadis, P. P. and Chandrakasan, A. 2000. Low power bus coding techniques considering inter-wire capacitances. Proceedings of the IEEE Custom Integrated Circuits
Conference, May 21-24, Orlando, FL, IEEE, pp. 507–510.
Sotiriadis, P. P. and Chandrakasan, A. 2002. A bus energy model for deep submicron
technology. IEEE Transaction on Very Large Scale Integration Systems, vol. 10, no. 3,
pp. 341–350.
Sridhara, S. R. and Shanbhag, N. R. 2005. Coding for system-on-chip networks: A unified framework. IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
vol. 13, no. 6, pp. 655–667.
Stan, M. R. and Burleson, W. P. 1995. Bus-invert coding for low-power I/O. IEEE
Transactions on Very Large Scale Integration (VLSI) System, vol. 3, no. 1, pp. 49–58.
Stratakos, A. 1998. High-efficiency low-voltage DC-DC conversion for portable applications. Ph D Thesis, University of California, Berkeley, CA.
Yoo, S. and Choi, K. 1999. Interleaving partial bus-invert Coding for low power reconfiguration of FPGAs. Proceedings of International Conference on VLSI and CAD,
October 26-27, Seoul, Republic of Korea, IEEE, pp. 549–552.
Yuan, C. P. and Cheng, Y. C. 2005. A voltage level converter circuit design with low
power consumption. Proceedings of International Conference on ASIC, October
24-27, Shanghai, People’s Republic of China, IEEE, pp. 358–359.
Zhang, Y., Lach, J., Skadron, K., and Stan, M. R. 2002. Odd/even bus invert with twophase transfer for buses with coupling. Proceedings of International Symposium on
Low Power Electronics and Design, Monterey, CA, IEEE, pp. 80–83.