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Low-Power Techniques for Network-on-Chip
Chuang, L. P., Chang, M. H., Huang, P. T., Kan, C. H., and Hwang, W. 2008. A
5.2mW all-digital fast-lock self-calibrated multiphase DLL. Proceedings of
International Symposium on Circuits and Systems, May 18-21, Seattle, WA, IEEE,
pp. 3342–3345.
Deogun, H. S., Rao, R. R., Sylvester, D., and Blaauw, D. 2004. Leakage- and crosstalkaware bus encoding for total power reduction. Proceedings of Design Automation
Conference, July 7-11, San Diego, CA, pp. 779–782.
Ghoneima, M. and Ismail, Y. 2004. Low power coupling-based encoding for on-chip
buses. Proceedings of IEEE International Symposium on Circuits and Systems,
May 23-26, Vancouver, BC, Canada, IEEE, pp. 325–328.
Huang, P. T., Fang, W. L., Wang, Y. L., and Hwang, W. 2008. Low power and reliable
interconnection with self- corrected green coding scheme for network-on-chip.
ACM/IEEE International Symposium on Networks-on-Chip, April 7-10, Newcastle
upon Tyne, IEEE, pp. 77–83.
Kim, K., Baek, K., Shanbhag, N., Liu, C., and Kang, S. 2000. Coupling-driven signal
encoding scheme for low-power interface design. Proceedings of ICCAD, November
5-9, San Jose, CA, IEEE, pp. 318–321.
Lee, K., Lee. S. J., Kim, S. E., Choi, H. M., Kim, D., Kim, S., Lee, M. W., and Yoo,
H. J. 2004. A 51mW 1.6GHz on-chip network for low power heterogeneous
SoC platform. Proceedings of IEEE International Solid-State Circuits Conference,
February 15-19, San Francisco, CA, IEEE.
Lee, S. E. and Bagherzadeh, N. 2009. A variable frequency link for a power-aware
network-on-chip. Integration, the VLSI Journal, vol. 42, no. 4, pp. 479–485.
Lee, S. J., Kim, K., Kim, H., Cho, N., and Yoo, H. J. 2006. A network-on-chip with
3Gbps/wire serialized on-chip interconnect using adaptive control schemes.
Proceedings of Design Automation and Test in Europe, pp. 79–80.
Lee, S. J., Lee, K., and Yoo, H. J. 2005. Analysis and implementation of practical,
cost-effective networks on chips. IEEE Design & Test Computers, vol. 22, no. 5,
pp. 422–433.
Lu, Y. and Agarwal, V. D. 2007. Statistical leakage and timing optimization for submicron process variation. Proceedings of 20th VLSI Design and 6th Embedded Systems,
January 6-10, Bangalore, India, IEEE, pp. 439–444.
Matustani, H., Koibuchi, M., Ikebuchi, D., Usami, K., Nakamura, H., and Amano, H.
2010. Ultra fine-grained run-time power gating of on-chip routers for CMPs.
Proceedings of ACM/IEEE International Symposium on Networks-on-Chip, May 3-6,
Grenoble, France, IEEE, pp. 61–68.
Mullins, R. 2006. Minimising dynamic power consumption in on-chip networks.
Proceedings of International Symposium on System-on-Chip, November 14–16,
Tampere, Finland, IEEE, pp. 1–4.
Ogras, U. Y., Marculescu, R., Choudhary, P., and Marculescu, D. 2007. Voltagefrequency island partitioning for GALS-based networks-on-chip. Proceedings of
Design and Automation Conference, June 4-8, San Diego, CA, IEEE, pp. 110–115.
Shang, L., Peh, L. S., and Jha, N. K. 2003. Dynamic voltage scaling with links for power
optimization of interconnection networks. Proceedings of IEEE International
Conference on High-Performance Computer Architecture, February 8-12, Anaheim,
CA, IEEE, pp. 91–102.
Soteriou, V. and Peh, L.-S. 2004. Design-space exploration of power-aware on/off
interconnection networks. Proceedings of the IEEE International Conference on
Computer Design, October 11-13, San Jose, CA, IEEE, pp. 510–517.