188
Network-on-Chip
Micropower domain 3
Micropower domain 2
Micropower domain 1
Std.
cell
Std.
cell
Std.
cell
Std.
cell
Std.
cell
Std.
cell
Std.
cell
Std.
cell
Std.
cell
Std.
cell
Std.
cell
Std.
cell
ISO
cell
ISO
cell
Std.
cell
PS
PS
PS
VGND 1
VGND 2
VGND 3
VDD
GND
GND
VDD
Figure 6.20
Fine-grained power gating. ISO, isolation cell; PS, power switch; VGND, virtual ground.
only in VC buffers, assuming that temperature and core voltage are set to 25°C
and 1.20 V, respectively. It is also shown that the leakage power reduction can
be extended to 78.9% when runtime power gating is applied to VC buffers, VC
multiplexers, crossbar multiplexers, and output latches at the expense of 4%
performance penalty, assuming that the routers are working at 1 GHz.
6.5 Summary
This chapter provides a clear insight into standard low-power techniques in
NoC. Different system-level dynamic and leakage power reduction techniques
including power–performance trade-off in NoC platform have also been discussed. In spite of power–performance trade-off, system reliability is another
metric to address while lowering the supply voltage. With the decrease in supply voltage, the signal-to-noise ratio reduces, thereby creating an adverse effect
on BER. Chapter 7 will focus on the signal integrity and reliability challenges
in NoC routers and interconnection links at nanometer regime.
References
Benini, L. and Micheli, G. D. 2006. Networks on Chips: Technology and Tools. Morgan
Kaufmann Publishers, San Francisco, CA.
Benini, L., Siegel, P., and Micheli, G. D. 1994. Automated synthesis of gated clocks
for power reduction in sequential circuits. IEEE Design and Test of Computers,
pp. 32–41, IEEE.