VFI1
PE
PE
OC
OC
FIFO
FIFO
FIFO
FIFO
FIFO
FIFO
OC
OC
OC
OC
OC
OC
FIFO
FIFO
FIFO
FIFO
VFI2
Clock domain 1
Clock domain 2
187
Low-Power Techniques for Network-on-Chip
Figure 6.19
Illustration of the interface between two different voltage–frequency domains VFI1 and VFI2.
are transferred on a NoC, whereas the leakage power (or static power) is
consumed without any packet transfers as long as the NoC is powered on.
Since the NoC is the communication infrastructure of chip multiprocessing,
it must be always ready for the packet transfers at any workload so as not
to increase the communication latency; thus, a runtime power management
that dynamically stops the leakage current whenever possible is highly
required. This section highlights the work cited by Matustani et al. (2010) on
ultra-fine-grained runtime power gating of on-chip router. They partitioned
the mesh-based router architecture into several power domains such as virtual channel (VC) buffer for each flit, output latch for each flit, crossbar multiplexer, and VC multiplexer. Isolation cells are inserted to all output ports
of the synthesized netlist in order to hold the output values of the domain
when the power supply is stopped. The netlist of isolation cells is placed by
Synopsys Astro tool. They formed the virtual ground (VGND) lines and the
power switches are inserted between the VGND and ground (GND) lines by
Synopsys Design Cool Power tool as shown in Figure 6.20.
In this design, the authors used customized standard cells that have a
VGND port in 65-nm technology and modified that according to the cell
height. They showed that the area overhead for inserting isolation cells and
power switch in the overall design is 4.3%. There is another area overhead of
the customized standard cells against the original ones. The total area overhead increases to 15.9%. The authors also assumed that the wake-up latency
of each power domain is two, three, and four cycles when the target NoC is
operated at 667 MHz, 1 GHz, and 1.33 GHz, respectively. This assumption is a
little bit conservative, since the actual wake-up latencies have been observed
to be less than 3 ns. Experimental results show a reduction of average router
leakage power by 64.6% when applying the runtime power gating technique