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Network-on-Chip
scale the frequency and voltage of various VFIs in order to minimize energy
consumption. As a result, the advantages of both NoC and VFI design styles
can be exploited simultaneously. This section focuses on the work cited by
Ogras et al. (2007) on power management using VFIs.
The design of NoCs with multiple VFIs involves a number of critical steps.
First, the granularity (i.e., the number of different VFIs) and chip partitioning
into VFIs need to be determined. While a NoC architecture where each processing/storage element constitutes a separate VFI exhibits the largest potential savings for energy consumption, this solution is very costly. Indeed, the
associated design complexity increases due to the overhead in implementing the mixed-clock/mixed-voltage FIFOs and voltage converters required
for communication across different VFIs, as well as the power distribution
network needed to cover multiple VFIs. Additionally, the VFI partitioning
needs to be performed together with assigning the supply and threshold
voltages and the corresponding clock speeds to each VFI. The energy overhead of adding one additional voltage–frequency island to an already existing design can be written as follows:
E VFI =E ClkGen +E Vconv + E
(6.14)
MixClkFifo
where:
E ClkGen is the energy overhead of generating additional clock signals
E Vconv denotes the energy consumption of the voltage level converters
E MixClkFifo is the overhead due to the mixed-clock/mixed-voltage FIFOs used
in interfaces
Besides energy, additional VFIs exhibit area and implementation overheads,
such as routing multiple power distribution networks. The maximum number of VFIs is assumed to be a constraint. To connect a node in a VFI with
another node residing in a different VFI, all data and control signals need to
be converted from one frequency/voltage domain to another. For this purpose, a mixed-clock/mixed-voltage interfaces using FIFOs are implemented,
which are natural candidates for converting the signals from one VFI to
another, as shown in Figure 6.19.
To find the optimum number of VFIs, Ogras et al. (2007) started their
experiment with 16 VFIs in a 4 × 4 mesh-based NoC structure. Then, it proceeds by merging the islands until a single island is obtained; as such, it
evaluates all possible levels of VFI granularity. Finally, based on different
applications, they concluded that two to three VFIs in NoC context provide
better power–performance trade-offs than its single-voltage, single-clock frequency counterpart.
6.4.4 runtime Power gating
The power consumption is classified into dynamic switching power and
static leakage power. The switching power is consumed only when packets