100
10
Relative delay
Gate delay
(fan-out of 4)
Local
(scaled)
Global with
repeaters
Global without
repeaters
250
0.1
180
Process technology node (nm)
130
90
65
45 32
2
Network-on-Chip
Usage of segmented bus architecture where a shared bus is segmented to
multiple buses using bridges also suffers from the same problem of bandwidth sharing. There is also a problem of distributing a synchronous clock
signal over the whole chip. In deep submicron (DSM) technologies, according to the International Technology Roadmap for Semiconductors (ITRS)
report (ITRS 2001), the delay of local wires and logic gates reduces with
every process generation, whereas global wire delay increases exponentially, or at best linearly, by inserting repeaters as shown in Figure 1.1. For a
relatively long bus, this delay is significant due to its high intrinsic parasitic
resistance and capacitance. As the IP blocks are connected to the bus, they
will add more capacitance to it, which may enhance the delay. In ultra-DSM
processes, it has been observed that long wires mostly fall in the critical
path of the design (Sylvester and Keutzer 2000; Kapur et al. 2002). The long
wires in DSM regime also introduce many signal integrity problems, such
as crosstalk noise, crosstalk delay, IR drop, and electromagnetic interference
(EMI). Moreover, the power consumption of the global wires along with
their drivers and repeaters can be a significant portion of the overall SoC
power budget. Therefore, in DSM technologies, on-chip communication
efficiency has become one of the key factors determining the overall system
performance and cost. The major challenge, SoC researchers face today, is
to come up with structured, scalable, reusable, and high-performance interconnection architectures.
Figure 1.1
Projected relative delay for local and global wires and for logic gates at different technologies.
(Data from ITRS, International technology roadmap for semiconductors, Technical report,
International Technology Roadmap for Semiconductors, 2001.)
10
Relative delay
Gate delay
(fan-out of 4)
Local
(scaled)
Global with
repeaters
Global without
repeaters
250
0.1
180
Process technology node (nm)
130
90
65
45 32
2
Network-on-Chip
Usage of segmented bus architecture where a shared bus is segmented to
multiple buses using bridges also suffers from the same problem of bandwidth sharing. There is also a problem of distributing a synchronous clock
signal over the whole chip. In deep submicron (DSM) technologies, according to the International Technology Roadmap for Semiconductors (ITRS)
report (ITRS 2001), the delay of local wires and logic gates reduces with
every process generation, whereas global wire delay increases exponentially, or at best linearly, by inserting repeaters as shown in Figure 1.1. For a
relatively long bus, this delay is significant due to its high intrinsic parasitic
resistance and capacitance. As the IP blocks are connected to the bus, they
will add more capacitance to it, which may enhance the delay. In ultra-DSM
processes, it has been observed that long wires mostly fall in the critical
path of the design (Sylvester and Keutzer 2000; Kapur et al. 2002). The long
wires in DSM regime also introduce many signal integrity problems, such
as crosstalk noise, crosstalk delay, IR drop, and electromagnetic interference
(EMI). Moreover, the power consumption of the global wires along with
their drivers and repeaters can be a significant portion of the overall SoC
power budget. Therefore, in DSM technologies, on-chip communication
efficiency has become one of the key factors determining the overall system
performance and cost. The major challenge, SoC researchers face today, is
to come up with structured, scalable, reusable, and high-performance interconnection architectures.
Figure 1.1
Projected relative delay for local and global wires and for logic gates at different technologies.
(Data from ITRS, International technology roadmap for semiconductors, Technical report,
International Technology Roadmap for Semiconductors, 2001.)