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Introduction

1.1 System-on-Chip Integration and Its Challenges
Continuous reduction in time to market, required by the multimedia and
consumer electronics commodities, makes full-custom design inappropriate. It has led to the design based on reuse of intellectual property (IP)
cores. With the growing complexity in consumer-embedded products, a
single-chip implementation integrating numerous IP cores performing various functions and possibly operating at different clock frequencies is now
a well-established one. Such an implementation is conveniently known as
system-on-chip (SoC). Depending on application domains and versatility, SoC
can be classified into two categories: (1) general-purpose multiprocessor SoC
(MPSoC) and (2) application-specific SoC.
Improving the performance and efficiency of a traditional large uniprocessor architecture is no longer achievable, thus enhancing the demand
for parallel processing. This, in turn, has resulted in a revolution in microprocessor architecture—chip multiprocessing (CMP) system. For boosting
up the performance of CMP-based systems, researchers have adopted SoC
platform to build a general-purpose MPSoC for supporting a wide range of
applications. This type of SoC is categorized by having a homogeneous set
of processing elements and storage arrays. Application-specific SoC, as the
name suggests, is dedicated to a specific application. This type of SoC, in
many cases, contains heterogeneous processing elements (e.g., processors,
controllers, and digital signal processors) and a number of domain-specific
hardware accelerators. This heterogeneity may lead to a specific traffic pattern requirement. Hence, a prior knowledge of traffic pattern is required
when the system is designed.
Shared medium arbitrated bus is the commonly used communication backbone in modern SoCs. Although this architecture has the advantages of simple topology, extensibility, and low area cost, a shared bus allows only one
communication at a time that may block all other buses in the hierarchy. Thus,
bus-based SoC does not scale the system performance with the number of
cores attached. Its bandwidth is also shared by all the cores (Grecu et al. 2004).
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