3
Introduction
1.2 SoC to Network-on-Chip: A Paradigm Shift
Several research groups from academia and industry have started to find
out the communication backbone of next-generation many-core-based SoCs
for supporting the new inter-core communication demands. Point-to-point
dedicated links can be a good alternative to global bus for a limited number
of cores in a SoC in terms of bandwidth, latency, and power consumption.
However, the number of links needed increases exponentially as the number
of cores increases. Thus, for a large system, it may create a routing problem
(Bjerregaard and Mahadevan 2006). A centralized crossbar switch overcomes
some of the limitations of the buses. Again, connecting large number of cores
to a single switch is not very effective as it is not ultimately scalable and,
thus, is an intermediate solution only (Bjerregaard and Mahadevan 2006).
At the system level, up to a certain number of cores on a single chip, the performance of traditional bus-based SoCs are expected to be satisfactory. But
in a many-core regime, as the number of cores residing on a SoC increases
significantly, it has a profound effect in shifting the focus from computation
to communication.
To overcome the above-mentioned problems, several research groups have
started to investigate systematic platform-based approaches to design the
communication backbone of MPSoC. On-chip interconnection network is
one solution to integrate IPs in complex SoCs. Network-on-chip (NoC) has
emerged as the viable alternative for the design of modular and scalable
communication architectures. The IP cores communicate with each other via
the router-based network. A core is attached to a router through a network
interface (NI) module (Benini and Micheli 2002). The network is used for
packet-switched on-chip communication among routers, whereas the NIs
enable seamless communication between various cores and the network.
The need for global synchronization can thus disappear. NoC supports the
globally asynchronous locally synchronous (GALS) style for multicore communication in SoCs.
The concept of on-chip network has been borrowed from off-chip interconnection networks where a single router is implemented per chip (Gratz et al.
2006). The bandwidth of off-chip networks is typically lower than that of
on-chip networks. Off-chip networks are constrained by bit width, as each
extra bit incurs one more pin. Also, the off-chip routers need to be connected
by explicit board traces. This affects the overall system latency and aggravates the synchronization problem (Jerger and Peh 2009).
The introduction of on-chip networks in SoC design is an evolution of bus
interconnect technology. Figure 1.2 shows a NoC structure where heterogeneous IP cores (CPU, DSP, etc.) communicate with each other via a network
and NI modules. The function of NI is to isolate the computation from communication. The network consists of switches (routers) and point-to-point
Introduction
1.2 SoC to Network-on-Chip: A Paradigm Shift
Several research groups from academia and industry have started to find
out the communication backbone of next-generation many-core-based SoCs
for supporting the new inter-core communication demands. Point-to-point
dedicated links can be a good alternative to global bus for a limited number
of cores in a SoC in terms of bandwidth, latency, and power consumption.
However, the number of links needed increases exponentially as the number
of cores increases. Thus, for a large system, it may create a routing problem
(Bjerregaard and Mahadevan 2006). A centralized crossbar switch overcomes
some of the limitations of the buses. Again, connecting large number of cores
to a single switch is not very effective as it is not ultimately scalable and,
thus, is an intermediate solution only (Bjerregaard and Mahadevan 2006).
At the system level, up to a certain number of cores on a single chip, the performance of traditional bus-based SoCs are expected to be satisfactory. But
in a many-core regime, as the number of cores residing on a SoC increases
significantly, it has a profound effect in shifting the focus from computation
to communication.
To overcome the above-mentioned problems, several research groups have
started to investigate systematic platform-based approaches to design the
communication backbone of MPSoC. On-chip interconnection network is
one solution to integrate IPs in complex SoCs. Network-on-chip (NoC) has
emerged as the viable alternative for the design of modular and scalable
communication architectures. The IP cores communicate with each other via
the router-based network. A core is attached to a router through a network
interface (NI) module (Benini and Micheli 2002). The network is used for
packet-switched on-chip communication among routers, whereas the NIs
enable seamless communication between various cores and the network.
The need for global synchronization can thus disappear. NoC supports the
globally asynchronous locally synchronous (GALS) style for multicore communication in SoCs.
The concept of on-chip network has been borrowed from off-chip interconnection networks where a single router is implemented per chip (Gratz et al.
2006). The bandwidth of off-chip networks is typically lower than that of
on-chip networks. Off-chip networks are constrained by bit width, as each
extra bit incurs one more pin. Also, the off-chip routers need to be connected
by explicit board traces. This affects the overall system latency and aggravates the synchronization problem (Jerger and Peh 2009).
The introduction of on-chip networks in SoC design is an evolution of bus
interconnect technology. Figure 1.2 shows a NoC structure where heterogeneous IP cores (CPU, DSP, etc.) communicate with each other via a network
and NI modules. The function of NI is to isolate the computation from communication. The network consists of switches (routers) and point-to-point