184
Network-on-Chip
clock period of the original clock frequency, and the link control function is
performed in each control period.
6.4.2.4 Results and Discussions
The DFS link characteristics for each boosting clock frequency are obtained
by simulation under the given workload (see Table 6.3). The 1× boosting
router finishes the entire packet transmission in 24.34 µs, spending more
time than 2× and 4× boosting routers. It also has the highest average and
peak latency. The 2× boosting router reduces the average latency by about
81% at the expense of 16% more dynamic power in contrast to the 1× boosting
router. Similarly, the 4× boosting router is much better compared to the 1×
boosting router in terms of latency; however, it consumes 21% more dynamic
power, reducing the average latency to 87%. It also reduces the average
latency around 32% at the expense of only 5.1% more dynamic power in comparison with the 2× boosting router. These experimental results demonstrate
the feasibility of clock boosting router for the DFS link for a power-aware
on-chip interconnection network in a NoC platform.
Table 6.4 summarizes the experimental results of the history-based DFS
policy varying the control period from 8 to 128 cycles of the 1× clock. DFS
policy enables the use of an intermediate value for power consumption
between 1× and 2× clock boosting routers. For instance, power consumption
of DFS with eight control periods consumes 2.09 mW, whereas 1× and 2×
TABLe 6.3
Characteristic of the DFS Link with the Workload
Boost Clock
(MHz)
Peak Latency
(ns/flit)
Average
Latency
(ns/flit)
End Time
(μs)
Dynamic
Power (mW)
Leakage
Power (mW)
Total Power
(mW)
100 (1×)
367
81.2
24.34
1.69
0.16
1.85
200 (2×)
97
15.3
24.06
1.96
0.16
2.12
400 (4×)
61
10.4
24.05
2.06
0.16
2.22
TABLe 6.4
Experimental Results of the History-Based DFS Varying Control Period
Control
Peak
Average
Period
Latency
Latency
End Time
Dynamic
Leakage
Total Power
(cycle)
(ns/flit)
(ns/flit)
(µs)
Power (mW)
Power (mW)
(mW)
8
116
24.30
24.05
1.93
0.16
2.09
16
146
25.20
24.05
1.91
0.16
2.07
32
187
27.60
24.23
1.90
0.16
2.06
64
242
33.20
24.34
1.88
0.16
2.04
128
265
48.21
24.05
1.91
0.16
2.07
Network-on-Chip
clock period of the original clock frequency, and the link control function is
performed in each control period.
6.4.2.4 Results and Discussions
The DFS link characteristics for each boosting clock frequency are obtained
by simulation under the given workload (see Table 6.3). The 1× boosting
router finishes the entire packet transmission in 24.34 µs, spending more
time than 2× and 4× boosting routers. It also has the highest average and
peak latency. The 2× boosting router reduces the average latency by about
81% at the expense of 16% more dynamic power in contrast to the 1× boosting
router. Similarly, the 4× boosting router is much better compared to the 1×
boosting router in terms of latency; however, it consumes 21% more dynamic
power, reducing the average latency to 87%. It also reduces the average
latency around 32% at the expense of only 5.1% more dynamic power in comparison with the 2× boosting router. These experimental results demonstrate
the feasibility of clock boosting router for the DFS link for a power-aware
on-chip interconnection network in a NoC platform.
Table 6.4 summarizes the experimental results of the history-based DFS
policy varying the control period from 8 to 128 cycles of the 1× clock. DFS
policy enables the use of an intermediate value for power consumption
between 1× and 2× clock boosting routers. For instance, power consumption
of DFS with eight control periods consumes 2.09 mW, whereas 1× and 2×
TABLe 6.3
Characteristic of the DFS Link with the Workload
Boost Clock
(MHz)
Peak Latency
(ns/flit)
Average
Latency
(ns/flit)
End Time
(μs)
Dynamic
Power (mW)
Leakage
Power (mW)
Total Power
(mW)
100 (1×)
367
81.2
24.34
1.69
0.16
1.85
200 (2×)
97
15.3
24.06
1.96
0.16
2.12
400 (4×)
61
10.4
24.05
2.06
0.16
2.22
TABLe 6.4
Experimental Results of the History-Based DFS Varying Control Period
Control
Peak
Average
Period
Latency
Latency
End Time
Dynamic
Leakage
Total Power
(cycle)
(ns/flit)
(ns/flit)
(µs)
Power (mW)
Power (mW)
(mW)
8
116
24.30
24.05
1.93
0.16
2.09
16
146
25.20
24.05
1.91
0.16
2.07
32
187
27.60
24.23
1.90
0.16
2.06
64
242
33.20
24.34
1.88
0.16
2.04
128
265
48.21
24.05
1.91
0.16
2.07